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[MIPS] tlbex.c: use __cacheline_aligned instead of __tlb_handler_align

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Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Franck Bui-Huu 2007-10-18 09:11:16 +02:00 committed by Ralf Baechle
parent f49b94d8c1
commit cbdbe07f9d
1 changed files with 3 additions and 6 deletions
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9
arch/mips/mm/tlbex.c
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@ -1391,18 +1391,15 @@ static void __init build_r4000_tlb_refill_handler(void)
extern void tlb_do_page_fault_0(void);
extern void tlb_do_page_fault_1(void);
#define __tlb_handler_align \
__attribute__((__aligned__(1 << CONFIG_MIPS_L1_CACHE_SHIFT)))
/*
* 128 instructions for the fastpath handler is generous and should
* never be exceeded.
*/
#define FASTPATH_SIZE 128
u32 __tlb_handler_align handle_tlbl[FASTPATH_SIZE];
u32 __tlb_handler_align handle_tlbs[FASTPATH_SIZE];
u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE];
u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned;
u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned;
u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned;
static void __init
iPTE_LW(u32 **p, struct label **l, unsigned int pte, unsigned int ptr)