msm: pcie: add support to enable common clk config for EP
Add support to enable the common clock configuration for the endpoint. Change-Id: I9f6c33eb6cfa032837a07e437f349a7c1a60704c Signed-off-by: Tony Truong <truong@codeaurora.org>
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@ -56,6 +56,7 @@ Optional Properties:
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- qcom,l1ss-supported: L1 sub-states (L1ss) is supported.
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- qcom,aux-clk-sync: The AUX clock is synchronous to the Core clock to
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support L1ss.
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- qcom,common-clk-en: Enables the common clock configuration for the endpoint.
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- qcom,n-fts: The number of fast training sequences sent when the link state
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is changed from L0s to L0.
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- qcom,ep-wakeirq: The endpoint will issue wake signal when it is up, and the
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@ -493,6 +493,7 @@ struct msm_pcie_dev_t {
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bool l0s_supported;
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bool l1_supported;
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bool l1ss_supported;
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bool common_clk_en;
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bool aux_clk_sync;
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uint32_t n_fts;
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bool ext_ref_clk;
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@ -1220,6 +1221,8 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev)
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dev->l1_supported ? "" : "not");
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pr_alert("l1ss_supported is %s supported\n",
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dev->l1ss_supported ? "" : "not");
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pr_alert("common_clk_en is %d\n",
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dev->common_clk_en);
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pr_alert("aux_clk_sync is %d\n",
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dev->aux_clk_sync);
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pr_alert("ext_ref_clk is %d\n",
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@ -2772,6 +2775,19 @@ static void msm_pcie_config_link_state(struct msm_pcie_dev_t *dev)
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dev->rc_idx, ep_link_cap_offset);
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}
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if (dev->common_clk_en) {
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msm_pcie_write_mask(dev->conf + ep_link_ctrlstts_offset,
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0, BIT(6));
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if (dev->shadow_en)
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dev->ep_shadow[0][ep_link_ctrlstts_offset / 4] =
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readl_relaxed(dev->conf +
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ep_link_ctrlstts_offset);
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PCIE_DBG2(dev, "EP's CAP_LINKCTRLSTATUS:0x%x\n",
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readl_relaxed(dev->conf + ep_link_ctrlstts_offset));
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}
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if (dev->l0s_supported) {
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msm_pcie_write_mask(dev->dm_core + PCIE20_CAP_LINKCTRLSTATUS,
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0, BIT(0));
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@ -4470,6 +4486,14 @@ static int msm_pcie_probe(struct platform_device *pdev)
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"qcom,l1ss-supported");
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PCIE_DBG(&msm_pcie_dev[rc_idx], "L1ss is %s supported.\n",
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msm_pcie_dev[rc_idx].l1ss_supported ? "" : "not");
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msm_pcie_dev[rc_idx].common_clk_en =
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of_property_read_bool((&pdev->dev)->of_node,
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"qcom,common-clk-en");
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PCIE_DBG(&msm_pcie_dev[rc_idx], "Common clock is %s enabled.\n",
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msm_pcie_dev[rc_idx].common_clk_en ? "" : "not");
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msm_pcie_dev[rc_idx].aux_clk_sync =
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of_property_read_bool((&pdev->dev)->of_node,
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"qcom,aux-clk-sync");
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msm_pcie_dev[rc_idx].aux_clk_sync =
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of_property_read_bool((&pdev->dev)->of_node,
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"qcom,aux-clk-sync");
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