Piteball
/
android_kernel_samsung_msm8976
mirror of https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
1
1
Fork 0
Code Issues Projects Releases Wiki Activity

crypto: msm: Add new parameter to pass ce frequency 

Crypto operating frequency varies from target to target. So platform
specific data needs to provide the value.

Change-Id: Icea908e958453444ba5a8e882664c8ca43e305e4
Signed-off-by: Mallikarjuna Reddy Amireddy <mamire@codeaurora.org>
This commit is contained in:
Mallikarjuna Reddy Amireddy 2014-09-12 19:49:11 +05:30
parent c5c19c1079
commit daae47365c
13 changed files with 43 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/crypto/msm/qcedev.txt
View File

@ -13,6 +13,7 @@ Required properties:
- qcom,msm_bus,num_paths: The paths for source and destination ports
- qcom,msm_bus,vectors: Vectors for bus topology.
- qcom,ce-device: Device number.
- qcom,ce-opp-freq: indicates the CE operating frequency in Hz, changes from target to target.
Optional properties:
- qcom,ce-hw-shared : optional, indicates if the hardware is shared between EE.
@ -37,4 +38,5 @@ Example:
qcom,msm-bus,vectors-KBps =
<56 512 0 0>,
<56 512 3936000 393600>,
qcom,ce-opp-freq = <100000000>;
};

3
Documentation/devicetree/bindings/crypto/msm/qcota.txt
View File

@ -9,6 +9,7 @@ Required properties:
- qcom,ce-hw-instance : should contain crypto HW instance.
- qcom,ce-device: Unique QCOTA device identifier. 0 for first
instance, 1 for second instance, n-1 for n-th instance.
- qcom,ce-opp-freq: indicates the CE operating frequency in Hz, changes from target to target.
Optional properties:
- qcom,support-core-clk-only : optional, indicates if the HW supports single crypto core clk.
@ -24,6 +25,7 @@ Example:
qcom,bam-pipe-pair = <1>;
qcom,ce-hw-instance = <2>;
qcom,ce-device = <0>;
qcom,ce-opp-freq = <100000000>;
};
qcom,qcota@fe0c0000 {
@ -35,4 +37,5 @@ Example:
qcom,bam-pipe-pair = <1>;
qcom,ce-hw-instance = <4>;
qcom,ce-device = <1>;
qcom,ce-opp-freq = <100000000>;
};

2
Documentation/devicetree/bindings/crypto/msm/qcrypto.txt
View File

@ -13,6 +13,7 @@ Required properties:
- qcom,msm_bus,num_paths: The paths for source and destination ports
- qcom,msm_bus,vectors: Vectors for bus topology.
- qcom,ce-device: Device number.
- qcom,ce-opp-freq: indicates the CE operating frequency in Hz, changes from target to target.
Optional properties:
- qcom,ce-hw-shared : optional, indicates if the hardware is shared between EE.
@ -44,4 +45,5 @@ Example:
qcom,msm-bus,vectors-KBps =
<56 512 0 0>,
<56 512 3936000 393600>,
qcom,ce-opp-freq = <100000000>;
};

2
arch/arm/boot/dts/qcom/apq8084.dtsi
View File

@ -681,6 +681,7 @@
qcom,msm-bus,vectors-KBps =
<56 512 0 0>,
<56 512 3936000 393600>;
qcom,ce-opp-freq = <100000000>;
};
qcom,qcrypto@fd444000 {
@ -702,6 +703,7 @@
qcom,msm-bus,vectors-KBps =
<56 512 0 0>,
<56 512 3936000 393600>;
qcom,ce-opp-freq = <100000000>;
};
wcd9xxx_intc: wcd9xxx-irq {

3
arch/arm/boot/dts/qcom/fsm9900.dtsi
View File

@ -654,6 +654,7 @@
qcom,bam-pipe-pair = <1>;
qcom,ce-hw-instance = <1>;
qcom,ce-device = <0>;
qcom,ce-opp-freq = <100000000>;
};
qcom,qcrypto@fe040000 {
compatible = "qcom,qcrypto";
@ -664,6 +665,7 @@
qcom,bam-pipe-pair = <1>;
qcom,ce-hw-instance = <6>;
qcom,ce-device = <1>;
qcom,ce-opp-freq = <100000000>;
};
qcom,qcrypto@fe000000 {
compatible = "qcom,qcrypto";
@ -674,6 +676,7 @@
qcom,bam-pipe-pair = <1>;
qcom,ce-hw-instance = <7>;
qcom,ce-device = <2>;
qcom,ce-opp-freq = <100000000>;
};
qcom,qcota@fe140000 {

2
arch/arm/boot/dts/qcom/msm8226.dtsi
View File

@ -1384,6 +1384,7 @@
qcom,msm-bus,vectors-KBps =
<55 512 0 0>,
<55 512 3936000 393600>;
qcom,ce-opp-freq = <100000000>;
};
qcom,qcedev@fd400000 {
@ -1403,6 +1404,7 @@
qcom,msm-bus,vectors-KBps =
<55 512 0 0>,
<55 512 3936000 393600>;
qcom,ce-opp-freq = <100000000>;
};
cpu-pmu {

2
arch/arm/boot/dts/qcom/msm8610.dtsi
View File

@ -1162,6 +1162,7 @@
qcom,msm-bus,vectors-KBps =
<55 512 0 0>,
<55 512 393600 3936000>;
qcom,ce-opp-freq = <100000000>;
};
qcom,qcedev@fd400000 {
@ -1181,6 +1182,7 @@
qcom,msm-bus,vectors-KBps =
<55 512 0 0>,
<55 512 393600 3936000>;
qcom,ce-opp-freq = <100000000>;
};
cpu-pmu {

2
arch/arm/boot/dts/qcom/msm8909.dtsi
View File

@ -1383,6 +1383,7 @@
qcom,use-sw-aes-xts-algo;
qcom,use-sw-ahash-algo;
status = "disabled";
qcom,ce-opp-freq = <100000000>;
};
qcom_cedev: qcedev@720000 {
@ -1408,6 +1409,7 @@
clock-names = "core_clk_src", "core_clk",
"iface_clk", "bus_clk";
status = "disabled";
qcom,ce-opp-freq = <100000000>;
};
qcom_seecom: qseecom@86000000 {

2
arch/arm/boot/dts/qcom/msm8916.dtsi
View File

@ -686,6 +686,7 @@
qcom,use-sw-aes-xts-algo;
qcom,use-sw-ahash-algo;
status = "disabled";
qcom,ce-opp-freq = <100000000>;
};
qcom_cedev: qcedev@720000 {
@ -711,6 +712,7 @@
clock-names = "core_clk_src", "core_clk",
"iface_clk", "bus_clk";
status = "disabled";
qcom,ce-opp-freq = <100000000>;
};
qcom_seecom: qseecom@86000000 {

2
arch/arm/boot/dts/qcom/msm8939-common.dtsi
View File

@ -683,6 +683,7 @@
clock-names = "core_clk_src", "core_clk",
"iface_clk", "bus_clk";
status = "disabled";
qcom,ce-opp-freq = <100000000>;
};
qcom_cedev: qcedev@720000 {
@ -708,6 +709,7 @@
clock-names = "core_clk_src", "core_clk",
"iface_clk", "bus_clk";
status = "disabled";
qcom,ce-opp-freq = <100000000>;
};
qcom_seecom: qseecom@86000000 {

3
arch/arm/boot/dts/qcom/msm8974.dtsi
View File

@ -2215,6 +2215,7 @@
qcom,msm-bus,vectors-KBps =
<56 512 0 0>,
<56 512 3936000 393600>;
qcom,ce-opp-freq = <100000000>;
};
qcom,qcrypto@fd440000 {
@ -2236,6 +2237,7 @@
qcom,msm-bus,vectors-KBps =
<56 512 0 0>,
<56 512 3936000 393600>;
qcom,ce-opp-freq = <100000000>;
};
qcom,qcrypto1@fd440000 {
compatible = "qcom,qcrypto";
@ -2256,6 +2258,7 @@
qcom,msm-bus,vectors-KBps =
<56 512 0 0>,
<56 512 3936000 393600>;
qcom,ce-opp-freq = <100000000>;
};
qcom,usbbam@f9304000 {

5
arch/arm/boot/dts/qcom/msm8994.dtsi
View File

@ -2592,6 +2592,7 @@
qcom,use-sw-aes-ccm-algo;
qcom,use-sw-ahash-algo;
status = "disabled";
qcom,ce-opp-freq = <171430000>;
};
qcom_crypto2fde: qcrypto2fde@0xfd3c0000 {
@ -2619,6 +2620,7 @@
qcom,use-sw-aes-ccm-algo;
qcom,use-sw-ahash-algo;
status = "disabled";
qcom,ce-opp-freq = <171430000>;
};
qcom_crypto1pfe: qcrypto1pfe@fd440000 {
@ -2646,6 +2648,7 @@
qcom,use-sw-aes-ccm-algo;
qcom,use-sw-ahash-algo;
status = "disabled";
qcom,ce-opp-freq = <171430000>;
};
qcom_crypto2pfe: qcrypto2pfe@0xfd3c0000 {
@ -2673,6 +2676,7 @@
qcom,use-sw-aes-ccm-algo;
qcom,use-sw-ahash-algo;
status = "disabled";
qcom,ce-opp-freq = <171430000>;
};
qcom_cedev: qcedev@fd440000 {
@ -2696,6 +2700,7 @@
<&clock_rpm clk_gcc_ce2_axi_m_clk>;
qcom,support-core-clk-only;
status = "disabled";
qcom,ce-opp-freq = <171430000>;
};
qcom,qseecom@6500000 {

15
drivers/crypto/msm/qce50.c
View File

@ -41,6 +41,8 @@
#define CRYPTO_CONFIG_RESET 0xE001F
#define QCE_MAX_NUM_DSCR 0x500
#define QCE_SECTOR_SIZE 0x200
#define CE_CLK_100MHZ 100000000
#define CE_CLK_DIV 1000000
static DEFINE_MUTEX(bam_register_lock);
struct bam_registration_info {
@ -101,6 +103,7 @@ struct qce_device {
dma_addr_t phy_ota_src;
dma_addr_t phy_ota_dst;
unsigned int ota_size;
unsigned int ce_opp_freq_hz;
bool use_sw_aes_cbc_ecb_ctr_algo;
bool use_sw_aead_algo;
@ -5187,6 +5190,12 @@ static int __qce_get_device_tree_data(struct platform_device *pdev,
pr_err("Fail to get CE hw instance information.\n");
return -EINVAL;
}
if (of_property_read_u32((&pdev->dev)->of_node,
"qcom,ce-opp-freq",
&pce_dev->ce_opp_freq_hz)) {
pr_info("CE operating frequency is not defined, setting to default 100MHZ\n");
pce_dev->ce_opp_freq_hz = CE_CLK_100MHZ;
}
pce_dev->ce_sps.dest_pipe_index = 2 * pce_dev->ce_sps.pipe_pair_index;
pce_dev->ce_sps.src_pipe_index = pce_dev->ce_sps.dest_pipe_index + 1;
@ -5241,9 +5250,11 @@ static int __qce_init_clk(struct qce_device *pce_dev)
pce_dev->ce_core_src_clk = clk_get(pce_dev->pdev, "core_clk_src");
if (!IS_ERR(pce_dev->ce_core_src_clk)) {
rc = clk_set_rate(pce_dev->ce_core_src_clk, 171430000);
rc = clk_set_rate(pce_dev->ce_core_src_clk,
pce_dev->ce_opp_freq_hz);
if (rc) {
pr_err("Unable to set the core src clk @100Mhz.\n");
pr_err("Unable to set the core src clk @%uMhz.\n",
pce_dev->ce_opp_freq_hz/CE_CLK_DIV);
goto exit_put_core_src_clk;
}
} else {