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clk: qcom: gdsc: Add support to configure clk_dis_wait value 

The CLK_DIS_WAIT bits value may differ from the default value of 0x2.
Allow the value to be taken as input from device tree as parameter
'qcom,clk-dis-wait-val'.

Change-Id: I0a42eec47a563acf667fe6dad39fcd8314e4d590
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This commit is contained in:
Taniya Das 2015-07-24 13:55:20 +05:30 committed by Gerrit - the friendly Code Review server
parent 5b0ce1c3bd
commit dc1901c44b
2 changed files with 9 additions and 3 deletions
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2
Documentation/devicetree/bindings/regulator/gdsc-regulator.txt
View File

@ -30,6 +30,8 @@ Optional properties:
and root clk is active without sw being aware of its
state. The clock-name which denotes the root clock
should be named as "core_root_clk".
- qcom,clk-dis-wait-val: Input value for CLK_DIS_WAIT controls state transition
delay after halting clock in the collapsible core.
- reg-names: Names of the bases for the above "reg" registers.
Ex. "base", "domain_addr".

10
drivers/clk/qcom/gdsc.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -305,7 +305,7 @@ static int gdsc_probe(struct platform_device *pdev)
struct regulator_init_data *init_data;
struct resource *res;
struct gdsc *sc;
uint32_t regval;
uint32_t regval, clk_dis_wait_val = CLK_DIS_WAIT_VAL;
bool retain_mem, retain_periph, support_hw_trigger;
int i, ret;
@ -395,9 +395,13 @@ static int gdsc_probe(struct platform_device *pdev)
regval = readl_relaxed(sc->gdscr);
regval &= ~(HW_CONTROL_MASK | SW_OVERRIDE_MASK);
if (!of_property_read_u32(pdev->dev.of_node, "qcom,clk-dis-wait-val",
&clk_dis_wait_val))
clk_dis_wait_val = clk_dis_wait_val << 12;
/* Configure wait time between states. */
regval &= ~(EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK);
regval |= EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
regval |= EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | clk_dis_wait_val;
writel_relaxed(regval, sc->gdscr);
retain_mem = of_property_read_bool(pdev->dev.of_node,