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drivers: mfd: Add support for wcd9335 version 2.0 

Add support for wcd9335 version 2.0 and update the
register defaults accordingly based on the version.

Change-Id: I33038c1643b83ecd593891688c0ddf4a556b92ee
Signed-off-by: Phani Kumar Uppalapati <phaniu@codeaurora.org>
This commit is contained in:
Phani Kumar Uppalapati 2015-08-05 20:11:58 -07:00 committed by Gerrit - the friendly Code Review server
parent c842f20d67
commit e09ec6964c
6 changed files with 422 additions and 149 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

462
drivers/mfd/wcd9335-regmap.c
View File

@ -18,11 +18,291 @@
#include <linux/device.h>
#include "wcd9xxx-regmap.h"
static const struct reg_default wcd9335_1_x_defaults[] = {
{ WCD9335_CODEC_RPM_CLK_GATE , 0x03 },
{ WCD9335_CODEC_RPM_PWR_CPE_DRAM1_SHUTDOWN , 0x1f },
{ WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0 , 0x00 },
{ WCD9335_CHIP_TIER_CTRL_EFUSE_CTL , 0x00 },
{ WCD9335_DATA_HUB_DATA_HUB_RX0_INP_CFG , 0x00 },
{ WCD9335_DATA_HUB_DATA_HUB_RX1_INP_CFG , 0x00 },
{ WCD9335_DATA_HUB_DATA_HUB_RX2_INP_CFG , 0x00 },
{ WCD9335_DATA_HUB_DATA_HUB_RX3_INP_CFG , 0x00 },
{ WCD9335_CPE_SS_CPARMAD_BUFRDY_INT_PERIOD , 0x14 },
{ WCD9335_CPE_SS_SS_ERROR_INT_MASK , 0x3f },
{ WCD9335_SOC_MAD_AUDIO_IIR_CTL_VAL , 0x00 },
{ WCD9335_BIAS_VBG_FINE_ADJ , 0x55 },
{ WCD9335_SIDO_SIDO_CCL_2 , 0x6c },
{ WCD9335_SIDO_SIDO_CCL_3 , 0x2d },
{ WCD9335_SIDO_SIDO_CCL_8 , 0x6c },
{ WCD9335_SIDO_SIDO_CCL_10 , 0x6c },
{ WCD9335_SIDO_SIDO_DRIVER_2 , 0x77 },
{ WCD9335_SIDO_SIDO_DRIVER_3 , 0x77 },
{ WCD9335_SIDO_SIDO_TEST_2 , 0x00 },
{ WCD9335_MBHC_ZDET_ANA_CTL , 0x00 },
{ WCD9335_MBHC_FSM_DEBUG , 0xc0 },
{ WCD9335_TX_1_2_ATEST_REFCTL , 0x08 },
{ WCD9335_TX_3_4_ATEST_REFCTL , 0x08 },
{ WCD9335_TX_5_6_ATEST_REFCTL , 0x08 },
{ WCD9335_FLYBACK_VNEG_CTRL_1 , 0x67 },
{ WCD9335_FLYBACK_VNEG_CTRL_4 , 0x5f },
{ WCD9335_FLYBACK_VNEG_CTRL_9 , 0x50 },
{ WCD9335_FLYBACK_VNEG_DAC_CTRL_1 , 0x65 },
{ WCD9335_FLYBACK_VNEG_DAC_CTRL_4 , 0x40 },
{ WCD9335_RX_BIAS_HPH_PA , 0xaa },
{ WCD9335_RX_BIAS_HPH_LOWPOWER , 0x62 },
{ WCD9335_HPH_PA_CTL2 , 0x40 },
{ WCD9335_HPH_L_EN , 0x00 },
{ WCD9335_HPH_R_EN , 0x00 },
{ WCD9335_HPH_R_ATEST , 0x50 },
{ WCD9335_HPH_RDAC_LDO_CTL , 0x00 },
{ WCD9335_CDC_TX0_TX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_TX0_TX_PATH_CFG1 , 0x00 },
{ WCD9335_CDC_TX0_TX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_TX0_TX_PATH_SEC3 , 0x0c },
{ WCD9335_CDC_TX1_TX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_TX1_TX_PATH_CFG1 , 0x00 },
{ WCD9335_CDC_TX1_TX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_TX1_TX_PATH_SEC3 , 0x0c },
{ WCD9335_CDC_TX2_TX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_TX3_TX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_TX4_TX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_TX5_TX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_TX6_TX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_TX7_TX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_TX8_TX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_TX2_TX_PATH_CFG1 , 0x00 },
{ WCD9335_CDC_TX3_TX_PATH_CFG1 , 0x00 },
{ WCD9335_CDC_TX4_TX_PATH_CFG1 , 0x00 },
{ WCD9335_CDC_TX5_TX_PATH_CFG1 , 0x00 },
{ WCD9335_CDC_TX6_TX_PATH_CFG1 , 0x00 },
{ WCD9335_CDC_TX7_TX_PATH_CFG1 , 0x00 },
{ WCD9335_CDC_TX8_TX_PATH_CFG1 , 0x00 },
{ WCD9335_CDC_TX2_TX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_TX3_TX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_TX4_TX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_TX5_TX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_TX6_TX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_TX7_TX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_TX8_TX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_TX2_TX_PATH_SEC3 , 0x0c },
{ WCD9335_CDC_TX3_TX_PATH_SEC3 , 0x0c },
{ WCD9335_CDC_TX4_TX_PATH_SEC3 , 0x0c },
{ WCD9335_CDC_TX5_TX_PATH_SEC3 , 0x0c },
{ WCD9335_CDC_TX6_TX_PATH_SEC3 , 0x0c },
{ WCD9335_CDC_TX7_TX_PATH_SEC3 , 0x0c },
{ WCD9335_CDC_TX8_TX_PATH_SEC3 , 0x0c },
{ WCD9335_CDC_COMPANDER1_CTL7 , 0x0c },
{ WCD9335_CDC_COMPANDER2_CTL7 , 0x0c },
{ WCD9335_CDC_COMPANDER3_CTL7 , 0x0c },
{ WCD9335_CDC_COMPANDER4_CTL7 , 0x0c },
{ WCD9335_CDC_COMPANDER5_CTL7 , 0x0c },
{ WCD9335_CDC_COMPANDER6_CTL7 , 0x0c },
{ WCD9335_CDC_COMPANDER7_CTL7 , 0x0c },
{ WCD9335_CDC_COMPANDER8_CTL7 , 0x0c },
{ WCD9335_CDC_RX0_RX_PATH_CFG1 , 0x04 },
{ WCD9335_CDC_RX0_RX_PATH_MIX_CFG , 0x0e },
{ WCD9335_CDC_RX0_RX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_RX0_RX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_RX0_RX_PATH_MIX_SEC0 , 0x00 },
{ WCD9335_CDC_RX1_RX_PATH_CFG1 , 0x04 },
{ WCD9335_CDC_RX1_RX_PATH_MIX_CFG , 0x0e },
{ WCD9335_CDC_RX1_RX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_RX1_RX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_RX1_RX_PATH_MIX_SEC0 , 0x00 },
{ WCD9335_CDC_RX2_RX_PATH_CFG1 , 0x04 },
{ WCD9335_CDC_RX2_RX_PATH_MIX_CFG , 0x0e },
{ WCD9335_CDC_RX2_RX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_RX2_RX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_RX2_RX_PATH_MIX_SEC0 , 0x00 },
{ WCD9335_CDC_RX3_RX_PATH_CFG1 , 0x04 },
{ WCD9335_CDC_RX3_RX_PATH_MIX_CFG , 0x0e },
{ WCD9335_CDC_RX3_RX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_RX3_RX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_RX3_RX_PATH_MIX_SEC0 , 0x00 },
{ WCD9335_CDC_RX4_RX_PATH_CFG1 , 0x04 },
{ WCD9335_CDC_RX4_RX_PATH_MIX_CFG , 0x0e },
{ WCD9335_CDC_RX4_RX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_RX4_RX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_RX4_RX_PATH_MIX_SEC0 , 0x00 },
{ WCD9335_CDC_RX5_RX_PATH_CFG1 , 0x04 },
{ WCD9335_CDC_RX5_RX_PATH_MIX_CFG , 0x0e },
{ WCD9335_CDC_RX5_RX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_RX5_RX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_RX5_RX_PATH_MIX_SEC0 , 0x00 },
{ WCD9335_CDC_RX6_RX_PATH_CFG1 , 0x04 },
{ WCD9335_CDC_RX6_RX_PATH_MIX_CFG , 0x0e },
{ WCD9335_CDC_RX6_RX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_RX6_RX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_RX6_RX_PATH_MIX_SEC0 , 0x00 },
{ WCD9335_CDC_RX7_RX_PATH_CFG1 , 0x04 },
{ WCD9335_CDC_RX7_RX_PATH_MIX_CFG , 0x0e },
{ WCD9335_CDC_RX7_RX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_RX7_RX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_RX7_RX_PATH_MIX_SEC0 , 0x00 },
{ WCD9335_CDC_RX8_RX_PATH_CFG1 , 0x04 },
{ WCD9335_CDC_RX8_RX_PATH_MIX_CFG , 0x0e },
{ WCD9335_CDC_RX8_RX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_RX8_RX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_RX8_RX_PATH_MIX_SEC0 , 0x00 },
{ WCD9335_SPLINE_SRC0_CLK_RST_CTL_0 , 0x00 },
{ WCD9335_SPLINE_SRC1_CLK_RST_CTL_0 , 0x00 },
{ WCD9335_SPLINE_SRC2_CLK_RST_CTL_0 , 0x00 },
{ WCD9335_SPLINE_SRC3_CLK_RST_CTL_0 , 0x00 },
{ WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL , 0x00 },
{ WCD9335_TEST_DEBUG_NPL_DLY_TEST_1 , 0x00 },
{ WCD9335_TEST_DEBUG_NPL_DLY_TEST_2 , 0x00 },
};
static const struct reg_default wcd9335_2_0_defaults[] = {
{ WCD9335_CODEC_RPM_CLK_GATE , 0x07 },
{ WCD9335_CODEC_RPM_PWR_CPE_DRAM1_SHUTDOWN , 0x3f },
{ WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0 , 0x01 },
{ WCD9335_CHIP_TIER_CTRL_EFUSE_CTL , 0x10 },
{ WCD9335_DATA_HUB_DATA_HUB_RX0_INP_CFG , 0x08 },
{ WCD9335_DATA_HUB_DATA_HUB_RX1_INP_CFG , 0x08 },
{ WCD9335_DATA_HUB_DATA_HUB_RX2_INP_CFG , 0x08 },
{ WCD9335_DATA_HUB_DATA_HUB_RX3_INP_CFG , 0x08 },
{ WCD9335_CPE_SS_CPARMAD_BUFRDY_INT_PERIOD , 0x13 },
{ WCD9335_CPE_SS_SS_ERROR_INT_MASK , 0xff },
{ WCD9335_SOC_MAD_AUDIO_IIR_CTL_VAL , 0x40 },
{ WCD9335_BIAS_VBG_FINE_ADJ , 0xc5 },
{ WCD9335_SIDO_SIDO_CCL_2 , 0x92 },
{ WCD9335_SIDO_SIDO_CCL_3 , 0x35 },
{ WCD9335_SIDO_SIDO_CCL_8 , 0x6e },
{ WCD9335_SIDO_SIDO_CCL_10 , 0x6e },
{ WCD9335_SIDO_SIDO_DRIVER_2 , 0x55 },
{ WCD9335_SIDO_SIDO_DRIVER_3 , 0x55 },
{ WCD9335_SIDO_SIDO_TEST_2 , 0x0f },
{ WCD9335_MBHC_ZDET_ANA_CTL , 0x0f },
{ WCD9335_TX_1_2_ATEST_REFCTL , 0x0a },
{ WCD9335_TX_3_4_ATEST_REFCTL , 0x0a },
{ WCD9335_TX_5_6_ATEST_REFCTL , 0x0a },
{ WCD9335_FLYBACK_VNEG_CTRL_1 , 0xeb },
{ WCD9335_FLYBACK_VNEG_CTRL_4 , 0x7f },
{ WCD9335_FLYBACK_VNEG_CTRL_9 , 0x64 },
{ WCD9335_FLYBACK_VNEG_DAC_CTRL_1 , 0xed },
{ WCD9335_RX_BIAS_HPH_PA , 0x9a },
{ WCD9335_RX_BIAS_HPH_LOWPOWER , 0x82 },
{ WCD9335_HPH_PA_CTL2 , 0x50 },
{ WCD9335_HPH_L_EN , 0x80 },
{ WCD9335_HPH_R_EN , 0x80 },
{ WCD9335_HPH_R_ATEST , 0x54 },
{ WCD9335_HPH_RDAC_LDO_CTL , 0x33 },
{ WCD9335_CDC_TX0_TX_PATH_CFG0 , 0x10 },
{ WCD9335_CDC_TX0_TX_PATH_CFG1 , 0x02 },
{ WCD9335_CDC_TX0_TX_PATH_SEC2 , 0x01 },
{ WCD9335_CDC_TX0_TX_PATH_SEC3 , 0x3c },
{ WCD9335_CDC_TX1_TX_PATH_CFG0 , 0x10 },
{ WCD9335_CDC_TX1_TX_PATH_CFG1 , 0x02 },
{ WCD9335_CDC_TX1_TX_PATH_SEC2 , 0x01 },
{ WCD9335_CDC_TX1_TX_PATH_SEC3 , 0x3c },
{ WCD9335_CDC_TX2_TX_PATH_CFG0 , 0x10 },
{ WCD9335_CDC_TX3_TX_PATH_CFG0 , 0x10 },
{ WCD9335_CDC_TX4_TX_PATH_CFG0 , 0x10 },
{ WCD9335_CDC_TX5_TX_PATH_CFG0 , 0x10 },
{ WCD9335_CDC_TX6_TX_PATH_CFG0 , 0x10 },
{ WCD9335_CDC_TX7_TX_PATH_CFG0 , 0x10 },
{ WCD9335_CDC_TX8_TX_PATH_CFG0 , 0x10 },
{ WCD9335_CDC_TX2_TX_PATH_CFG1 , 0x02 },
{ WCD9335_CDC_TX3_TX_PATH_CFG1 , 0x02 },
{ WCD9335_CDC_TX4_TX_PATH_CFG1 , 0x02 },
{ WCD9335_CDC_TX5_TX_PATH_CFG1 , 0x02 },
{ WCD9335_CDC_TX6_TX_PATH_CFG1 , 0x02 },
{ WCD9335_CDC_TX7_TX_PATH_CFG1 , 0x02 },
{ WCD9335_CDC_TX8_TX_PATH_CFG1 , 0x02 },
{ WCD9335_CDC_TX2_TX_PATH_SEC2 , 0x01 },
{ WCD9335_CDC_TX3_TX_PATH_SEC2 , 0x01 },
{ WCD9335_CDC_TX4_TX_PATH_SEC2 , 0x01 },
{ WCD9335_CDC_TX5_TX_PATH_SEC2 , 0x01 },
{ WCD9335_CDC_TX6_TX_PATH_SEC2 , 0x01 },
{ WCD9335_CDC_TX7_TX_PATH_SEC2 , 0x01 },
{ WCD9335_CDC_TX8_TX_PATH_SEC2 , 0x01 },
{ WCD9335_CDC_TX2_TX_PATH_SEC3 , 0x3c },
{ WCD9335_CDC_TX3_TX_PATH_SEC3 , 0x3c },
{ WCD9335_CDC_TX4_TX_PATH_SEC3 , 0x3c },
{ WCD9335_CDC_TX5_TX_PATH_SEC3 , 0x3c },
{ WCD9335_CDC_TX6_TX_PATH_SEC3 , 0x3c },
{ WCD9335_CDC_TX7_TX_PATH_SEC3 , 0x3c },
{ WCD9335_CDC_TX8_TX_PATH_SEC3 , 0x3c },
{ WCD9335_CDC_COMPANDER1_CTL7 , 0x08 },
{ WCD9335_CDC_COMPANDER2_CTL7 , 0x08 },
{ WCD9335_CDC_COMPANDER3_CTL7 , 0x08 },
{ WCD9335_CDC_COMPANDER4_CTL7 , 0x08 },
{ WCD9335_CDC_COMPANDER5_CTL7 , 0x08 },
{ WCD9335_CDC_COMPANDER6_CTL7 , 0x08 },
{ WCD9335_CDC_COMPANDER7_CTL7 , 0x08 },
{ WCD9335_CDC_COMPANDER8_CTL7 , 0x08 },
{ WCD9335_CDC_RX0_RX_PATH_CFG1 , 0x44 },
{ WCD9335_CDC_RX0_RX_PATH_MIX_CFG , 0x1e },
{ WCD9335_CDC_RX0_RX_PATH_SEC0 , 0xfc },
{ WCD9335_CDC_RX0_RX_PATH_SEC1 , 0x08 },
{ WCD9335_CDC_RX0_RX_PATH_MIX_SEC0 , 0x08 },
{ WCD9335_CDC_RX1_RX_PATH_CFG1 , 0x44 },
{ WCD9335_CDC_RX1_RX_PATH_MIX_CFG , 0x1e },
{ WCD9335_CDC_RX1_RX_PATH_SEC0 , 0xfc },
{ WCD9335_CDC_RX1_RX_PATH_SEC1 , 0x08 },
{ WCD9335_CDC_RX1_RX_PATH_MIX_SEC0 , 0x08 },
{ WCD9335_CDC_RX2_RX_PATH_CFG1 , 0x44 },
{ WCD9335_CDC_RX2_RX_PATH_MIX_CFG , 0x1e },
{ WCD9335_CDC_RX2_RX_PATH_SEC0 , 0xfc },
{ WCD9335_CDC_RX2_RX_PATH_SEC1 , 0x08 },
{ WCD9335_CDC_RX2_RX_PATH_MIX_SEC0 , 0x08 },
{ WCD9335_CDC_RX3_RX_PATH_CFG1 , 0x44 },
{ WCD9335_CDC_RX3_RX_PATH_MIX_CFG , 0x1e },
{ WCD9335_CDC_RX3_RX_PATH_SEC0 , 0xfc },
{ WCD9335_CDC_RX3_RX_PATH_SEC1 , 0x08 },
{ WCD9335_CDC_RX3_RX_PATH_MIX_SEC0 , 0x08 },
{ WCD9335_CDC_RX4_RX_PATH_CFG1 , 0x44 },
{ WCD9335_CDC_RX4_RX_PATH_MIX_CFG , 0x1e },
{ WCD9335_CDC_RX4_RX_PATH_SEC0 , 0xfc },
{ WCD9335_CDC_RX4_RX_PATH_SEC1 , 0x08 },
{ WCD9335_CDC_RX4_RX_PATH_MIX_SEC0 , 0x08 },
{ WCD9335_CDC_RX5_RX_PATH_CFG1 , 0x44 },
{ WCD9335_CDC_RX5_RX_PATH_MIX_CFG , 0x1e },
{ WCD9335_CDC_RX5_RX_PATH_SEC0 , 0xfc },
{ WCD9335_CDC_RX5_RX_PATH_SEC1 , 0x08 },
{ WCD9335_CDC_RX5_RX_PATH_MIX_SEC0 , 0x08 },
{ WCD9335_CDC_RX6_RX_PATH_CFG1 , 0x44 },
{ WCD9335_CDC_RX6_RX_PATH_MIX_CFG , 0x1e },
{ WCD9335_CDC_RX6_RX_PATH_SEC0 , 0xfc },
{ WCD9335_CDC_RX6_RX_PATH_SEC1 , 0x08 },
{ WCD9335_CDC_RX6_RX_PATH_MIX_SEC0 , 0x08 },
{ WCD9335_CDC_RX7_RX_PATH_CFG1 , 0x44 },
{ WCD9335_CDC_RX7_RX_PATH_MIX_CFG , 0x1e },
{ WCD9335_CDC_RX7_RX_PATH_SEC0 , 0xfc },
{ WCD9335_CDC_RX7_RX_PATH_SEC1 , 0x08 },
{ WCD9335_CDC_RX7_RX_PATH_MIX_SEC0 , 0x08 },
{ WCD9335_CDC_RX8_RX_PATH_CFG1 , 0x44 },
{ WCD9335_CDC_RX8_RX_PATH_MIX_CFG , 0x1e },
{ WCD9335_CDC_RX8_RX_PATH_SEC0 , 0xfc },
{ WCD9335_CDC_RX8_RX_PATH_SEC1 , 0x08 },
{ WCD9335_CDC_RX8_RX_PATH_MIX_SEC0 , 0x08 },
{ WCD9335_SPLINE_SRC0_CLK_RST_CTL_0 , 0x20 },
{ WCD9335_SPLINE_SRC1_CLK_RST_CTL_0 , 0x20 },
{ WCD9335_SPLINE_SRC2_CLK_RST_CTL_0 , 0x20 },
{ WCD9335_SPLINE_SRC3_CLK_RST_CTL_0 , 0x20 },
{ WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL , 0x0c },
{ WCD9335_TEST_DEBUG_NPL_DLY_TEST_1 , 0x10 },
{ WCD9335_TEST_DEBUG_NPL_DLY_TEST_2 , 0x60 },
{ WCD9335_DATA_HUB_NATIVE_FIFO_SYNC , 0x00 },
{ WCD9335_DATA_HUB_NATIVE_FIFO_STATUS , 0x00 },
{ WCD9335_CPE_SS_TX_PP_BUF_INT_PERIOD , 0x60 },
{ WCD9335_CPE_SS_TX_PP_CFG , 0x3C },
{ WCD9335_CPE_SS_SVA_CFG , 0x00 },
{ WCD9335_MBHC_FSM_STATUS , 0x00 },
{ WCD9335_FLYBACK_CTRL_1 , 0x45 },
{ WCD9335_CDC_TX0_TX_PATH_SEC7 , 0x25 },
{ WCD9335_SPLINE_SRC0_STATUS , 0x00 },
{ WCD9335_SPLINE_SRC1_STATUS , 0x00 },
{ WCD9335_SPLINE_SRC2_STATUS , 0x00 },
{ WCD9335_SPLINE_SRC3_STATUS , 0x00 },
{ WCD9335_CDC_PROX_DETECT_PROX_CTL_REPEAT_PAT , 0x00 },
};
static const struct reg_default wcd9335_defaults[] = {
/* Page #0 registers */
{ WCD9335_PAGE0_PAGE_REGISTER , 0x00 },
{ WCD9335_CODEC_RPM_CLK_BYPASS , 0x00 },
{ WCD9335_CODEC_RPM_CLK_GATE , 0x03 },
{ WCD9335_CODEC_RPM_CLK_MCLK_CFG , 0x00 },
{ WCD9335_CODEC_RPM_RST_CTL , 0x00 },
{ WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL , 0x07 },
@ -30,17 +310,14 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_CODEC_RPM_PWR_CPE_DEEPSLP_2 , 0x00 },
{ WCD9335_CODEC_RPM_PWR_CPE_DEEPSLP_3 , 0x00 },
{ WCD9335_CODEC_RPM_PWR_CPE_IRAM_SHUTDOWN , 0x01 },
{ WCD9335_CODEC_RPM_PWR_CPE_DRAM1_SHUTDOWN , 0x1f },
{ WCD9335_CODEC_RPM_PWR_CPE_DRAM0_SHUTDOWN_1 , 0xff },
{ WCD9335_CODEC_RPM_PWR_CPE_DRAM0_SHUTDOWN_2 , 0xff },
{ WCD9335_CODEC_RPM_INT_MASK , 0x3f },
{ WCD9335_CODEC_RPM_INT_STATUS , 0x00 },
{ WCD9335_CODEC_RPM_INT_CLEAR , 0x00 },
{ WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0 , 0x00 },
{ WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE1 , 0x00 },
{ WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE2 , 0x07 },
{ WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE3 , 0x01 },
{ WCD9335_CHIP_TIER_CTRL_EFUSE_CTL , 0x00 },
{ WCD9335_CHIP_TIER_CTRL_EFUSE_TEST0 , 0x00 },
{ WCD9335_CHIP_TIER_CTRL_EFUSE_TEST1 , 0x00 },
{ WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0 , 0x00 },
@ -81,10 +358,6 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_DATA_HUB_DATA_HUB_RX_I2S_CTL , 0x0c },
{ WCD9335_DATA_HUB_DATA_HUB_TX_I2S_CTL , 0x0c },
{ WCD9335_DATA_HUB_DATA_HUB_I2S_CLK , 0x00 },
{ WCD9335_DATA_HUB_DATA_HUB_RX0_INP_CFG , 0x00 },
{ WCD9335_DATA_HUB_DATA_HUB_RX1_INP_CFG , 0x00 },
{ WCD9335_DATA_HUB_DATA_HUB_RX2_INP_CFG , 0x00 },
{ WCD9335_DATA_HUB_DATA_HUB_RX3_INP_CFG , 0x00 },
{ WCD9335_DATA_HUB_DATA_HUB_RX4_INP_CFG , 0x00 },
{ WCD9335_DATA_HUB_DATA_HUB_RX5_INP_CFG , 0x00 },
{ WCD9335_DATA_HUB_DATA_HUB_RX6_INP_CFG , 0x00 },
@ -360,7 +633,6 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_CPE_SS_OUTBOX2_ACK , 0x00 },
{ WCD9335_CPE_SS_EC_BUF_INT_PERIOD , 0x3c },
{ WCD9335_CPE_SS_US_BUF_INT_PERIOD , 0x60 },
{ WCD9335_CPE_SS_CPARMAD_BUFRDY_INT_PERIOD , 0x14 },
{ WCD9335_CPE_SS_CFG , 0x41 },
{ WCD9335_CPE_SS_US_EC_MUX_CFG , 0x00 },
{ WCD9335_CPE_SS_MAD_CTL , 0x00 },
@ -374,7 +646,6 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_CPE_SS_BACKUP_INT , 0x00 },
{ WCD9335_CPE_SS_STATUS , 0x00 },
{ WCD9335_CPE_SS_CPE_OCD_CFG , 0x00 },
{ WCD9335_CPE_SS_SS_ERROR_INT_MASK , 0x3f },
{ WCD9335_CPE_SS_SS_ERROR_INT_STATUS , 0x00 },
{ WCD9335_CPE_SS_SS_ERROR_INT_CLEAR , 0x00 },
{ WCD9335_SOC_MAD_MAIN_CTL_1 , 0x00 },
@ -388,7 +659,6 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_SOC_MAD_AUDIO_CTL_7 , 0x00 },
{ WCD9335_SOC_MAD_AUDIO_CTL_8 , 0x00 },
{ WCD9335_SOC_MAD_AUDIO_IIR_CTL_PTR , 0x00 },
{ WCD9335_SOC_MAD_AUDIO_IIR_CTL_VAL , 0x00 },
{ WCD9335_SOC_MAD_ULTR_CTL_1 , 0x00 },
{ WCD9335_SOC_MAD_ULTR_CTL_2 , 0x00 },
{ WCD9335_SOC_MAD_ULTR_CTL_3 , 0x00 },
@ -449,7 +719,6 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_ANA_MICB4 , 0x10 },
{ WCD9335_ANA_VBADC , 0x00 },
{ WCD9335_BIAS_CTL , 0x28 },
{ WCD9335_BIAS_VBG_FINE_ADJ , 0x55 },
{ WCD9335_CLOCK_TEST_CTL , 0x00 },
{ WCD9335_RCO_CTRL_1 , 0x44 },
{ WCD9335_RCO_CTRL_2 , 0x44 },
@ -470,32 +739,23 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_SIDO_SIDO_VCL_2 , 0x6c },
{ WCD9335_SIDO_SIDO_VCL_3 , 0x44 },
{ WCD9335_SIDO_SIDO_CCL_1 , 0x57 },
{ WCD9335_SIDO_SIDO_CCL_2 , 0x6c },
{ WCD9335_SIDO_SIDO_CCL_3 , 0x2d },
{ WCD9335_SIDO_SIDO_CCL_4 , 0x61 },
{ WCD9335_SIDO_SIDO_CCL_5 , 0x6d },
{ WCD9335_SIDO_SIDO_CCL_6 , 0x60 },
{ WCD9335_SIDO_SIDO_CCL_7 , 0x6f },
{ WCD9335_SIDO_SIDO_CCL_8 , 0x6c },
{ WCD9335_SIDO_SIDO_CCL_9 , 0x6e },
{ WCD9335_SIDO_SIDO_CCL_10 , 0x6c },
{ WCD9335_SIDO_SIDO_FILTER_1 , 0x92 },
{ WCD9335_SIDO_SIDO_FILTER_2 , 0x54 },
{ WCD9335_SIDO_SIDO_DRIVER_1 , 0x77 },
{ WCD9335_SIDO_SIDO_DRIVER_2 , 0x77 },
{ WCD9335_SIDO_SIDO_DRIVER_3 , 0x77 },
{ WCD9335_SIDO_SIDO_CAL_CODE_EXT_1 , 0x9c },
{ WCD9335_SIDO_SIDO_CAL_CODE_EXT_2 , 0x82 },
{ WCD9335_SIDO_SIDO_CAL_CODE_OUT_1 , 0x00 },
{ WCD9335_SIDO_SIDO_CAL_CODE_OUT_2 , 0x00 },
{ WCD9335_SIDO_SIDO_TEST_1 , 0x00 },
{ WCD9335_SIDO_SIDO_TEST_2 , 0x00 },
{ WCD9335_MBHC_CTL_1 , 0x32 },
{ WCD9335_MBHC_CTL_2 , 0x01 },
{ WCD9335_MBHC_PLUG_DETECT_CTL , 0x69 },
{ WCD9335_MBHC_ZDET_ANA_CTL , 0x00 },
{ WCD9335_MBHC_ZDET_RAMP_CTL , 0x00 },
{ WCD9335_MBHC_FSM_DEBUG , 0xc0 },
{ WCD9335_MBHC_TEST_CTL , 0x00 },
{ WCD9335_VBADC_SUBBLOCK_EN , 0xfe },
{ WCD9335_VBADC_IBIAS_FE , 0x54 },
@ -533,7 +793,6 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_TX_COM_TXFE_DIV_STOP_12P288M , 0xff },
{ WCD9335_TX_1_2_TEST_EN , 0xcc },
{ WCD9335_TX_1_2_ADC_IB , 0x09 },
{ WCD9335_TX_1_2_ATEST_REFCTL , 0x08 },
{ WCD9335_TX_1_2_TEST_CTL , 0x38 },
{ WCD9335_TX_1_2_TEST_BLK_EN , 0xff },
{ WCD9335_TX_1_2_TXFE_CLKDIV , 0x00 },
@ -541,7 +800,6 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_TX_1_2_SAR2_ERR , 0x00 },
{ WCD9335_TX_3_4_TEST_EN , 0xcc },
{ WCD9335_TX_3_4_ADC_IB , 0x09 },
{ WCD9335_TX_3_4_ATEST_REFCTL , 0x08 },
{ WCD9335_TX_3_4_TEST_CTL , 0x38 },
{ WCD9335_TX_3_4_TEST_BLK_EN , 0xff },
{ WCD9335_TX_3_4_TXFE_CLKDIV , 0x00 },
@ -549,7 +807,6 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_TX_3_4_SAR2_ERR , 0x00 },
{ WCD9335_TX_5_6_TEST_EN , 0xcc },
{ WCD9335_TX_5_6_ADC_IB , 0x09 },
{ WCD9335_TX_5_6_ATEST_REFCTL , 0x08 },
{ WCD9335_TX_5_6_TEST_CTL , 0x38 },
{ WCD9335_TX_5_6_TEST_BLK_EN , 0xff },
{ WCD9335_TX_5_6_TXFE_CLKDIV , 0x00 },
@ -569,19 +826,14 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_CLASSH_BUCK_SW_DRV_CNTL , 0x77 },
{ WCD9335_CLASSH_SPARE , 0x00 },
{ WCD9335_FLYBACK_EN , 0x4e },
{ WCD9335_FLYBACK_VNEG_CTRL_1 , 0x67 },
{ WCD9335_FLYBACK_VNEG_CTRL_2 , 0x45 },
{ WCD9335_FLYBACK_VNEG_CTRL_3 , 0x74 },
{ WCD9335_FLYBACK_VNEG_CTRL_4 , 0x5f },
{ WCD9335_FLYBACK_VNEG_CTRL_5 , 0x83 },
{ WCD9335_FLYBACK_VNEG_CTRL_6 , 0x98 },
{ WCD9335_FLYBACK_VNEG_CTRL_7 , 0xa9 },
{ WCD9335_FLYBACK_VNEG_CTRL_8 , 0x68 },
{ WCD9335_FLYBACK_VNEG_CTRL_9 , 0x50 },
{ WCD9335_FLYBACK_VNEG_DAC_CTRL_1 , 0x65 },
{ WCD9335_FLYBACK_VNEG_DAC_CTRL_2 , 0x50 },
{ WCD9335_FLYBACK_VNEG_DAC_CTRL_3 , 0xa6 },
{ WCD9335_FLYBACK_VNEG_DAC_CTRL_4 , 0x40 },
{ WCD9335_FLYBACK_TEST_CTL , 0x00 },
{ WCD9335_RX_AUX_SW_CTL , 0x00 },
{ WCD9335_RX_PA_AUX_IN_CONN , 0x00 },
@ -591,11 +843,9 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_RX_BIAS_EAR_DAC , 0xa0 },
{ WCD9335_RX_BIAS_EAR_AMP , 0xaa },
{ WCD9335_RX_BIAS_HPH_LDO , 0xa9 },
{ WCD9335_RX_BIAS_HPH_PA , 0xaa },
{ WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2 , 0x8a },
{ WCD9335_RX_BIAS_HPH_RDAC_LDO , 0x88 },
{ WCD9335_RX_BIAS_HPH_CNP1 , 0x86 },
{ WCD9335_RX_BIAS_HPH_LOWPOWER , 0x62 },
{ WCD9335_RX_BIAS_DIFFLO_PA , 0x80 },
{ WCD9335_RX_BIAS_DIFFLO_REF , 0x88 },
{ WCD9335_RX_BIAS_DIFFLO_LDO , 0x88 },
@ -614,16 +864,11 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_HPH_AUTO_CHOP , 0x12 },
{ WCD9335_HPH_CHOP_CTL , 0x83 },
{ WCD9335_HPH_PA_CTL1 , 0x46 },
{ WCD9335_HPH_PA_CTL2 , 0x40 },
{ WCD9335_HPH_L_EN , 0x00 },
{ WCD9335_HPH_L_TEST , 0x00 },
{ WCD9335_HPH_L_ATEST , 0x50 },
{ WCD9335_HPH_R_EN , 0x00 },
{ WCD9335_HPH_R_TEST , 0x00 },
{ WCD9335_HPH_R_ATEST , 0x50 },
{ WCD9335_HPH_RDAC_CLK_CTL1 , 0x99 },
{ WCD9335_HPH_RDAC_CLK_CTL2 , 0x9b },
{ WCD9335_HPH_RDAC_LDO_CTL , 0x00 },
{ WCD9335_HPH_RDAC_CHOP_CLK_LP_CTL , 0x00 },
{ WCD9335_HPH_REFBUFF_UHQA_CTL , 0xa8 },
{ WCD9335_HPH_REFBUFF_LP_CTL , 0x00 },
@ -693,119 +938,83 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_CDC_ANC1_FF_B_GAIN_CTL , 0x00 },
{ WCD9335_CDC_ANC1_FB_GAIN_CTL , 0x00 },
{ WCD9335_CDC_TX0_TX_PATH_CTL , 0x04 },
{ WCD9335_CDC_TX0_TX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_TX0_TX_PATH_CFG1 , 0x00 },
{ WCD9335_CDC_TX0_TX_VOL_CTL , 0x00 },
{ WCD9335_CDC_TX0_TX_PATH_192_CTL , 0x00 },
{ WCD9335_CDC_TX0_TX_PATH_192_CFG , 0x00 },
{ WCD9335_CDC_TX0_TX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_TX0_TX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_TX0_TX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_TX0_TX_PATH_SEC3 , 0x0c },
{ WCD9335_CDC_TX0_TX_PATH_SEC4 , 0x20 },
{ WCD9335_CDC_TX0_TX_PATH_SEC5 , 0x00 },
{ WCD9335_CDC_TX0_TX_PATH_SEC6 , 0x00 },
{ WCD9335_CDC_TX1_TX_PATH_CTL , 0x04 },
{ WCD9335_CDC_TX1_TX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_TX1_TX_PATH_CFG1 , 0x00 },
{ WCD9335_CDC_TX1_TX_VOL_CTL , 0x00 },
{ WCD9335_CDC_TX1_TX_PATH_192_CTL , 0x00 },
{ WCD9335_CDC_TX1_TX_PATH_192_CFG , 0x00 },
{ WCD9335_CDC_TX1_TX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_TX1_TX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_TX1_TX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_TX1_TX_PATH_SEC3 , 0x0c },
{ WCD9335_CDC_TX1_TX_PATH_SEC4 , 0x20 },
{ WCD9335_CDC_TX1_TX_PATH_SEC5 , 0x00 },
{ WCD9335_CDC_TX1_TX_PATH_SEC6 , 0x00 },
{ WCD9335_CDC_TX2_TX_PATH_CTL , 0x04 },
{ WCD9335_CDC_TX2_TX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_TX2_TX_PATH_CFG1 , 0x00 },
{ WCD9335_CDC_TX2_TX_VOL_CTL , 0x00 },
{ WCD9335_CDC_TX2_TX_PATH_192_CTL , 0x00 },
{ WCD9335_CDC_TX2_TX_PATH_192_CFG , 0x00 },
{ WCD9335_CDC_TX2_TX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_TX2_TX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_TX2_TX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_TX2_TX_PATH_SEC3 , 0x0c },
{ WCD9335_CDC_TX2_TX_PATH_SEC4 , 0x20 },
{ WCD9335_CDC_TX2_TX_PATH_SEC5 , 0x00 },
{ WCD9335_CDC_TX2_TX_PATH_SEC6 , 0x00 },
{ WCD9335_CDC_TX3_TX_PATH_CTL , 0x04 },
{ WCD9335_CDC_TX3_TX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_TX3_TX_PATH_CFG1 , 0x00 },
{ WCD9335_CDC_TX3_TX_VOL_CTL , 0x00 },
{ WCD9335_CDC_TX3_TX_PATH_192_CTL , 0x00 },
{ WCD9335_CDC_TX3_TX_PATH_192_CFG , 0x00 },
{ WCD9335_CDC_TX3_TX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_TX3_TX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_TX3_TX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_TX3_TX_PATH_SEC3 , 0x0c },
{ WCD9335_CDC_TX3_TX_PATH_SEC4 , 0x20 },
{ WCD9335_CDC_TX3_TX_PATH_SEC5 , 0x00 },
{ WCD9335_CDC_TX3_TX_PATH_SEC6 , 0x00 },
{ WCD9335_CDC_TX4_TX_PATH_CTL , 0x04 },
{ WCD9335_CDC_TX4_TX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_TX4_TX_PATH_CFG1 , 0x00 },
{ WCD9335_CDC_TX4_TX_VOL_CTL , 0x00 },
{ WCD9335_CDC_TX4_TX_PATH_192_CTL , 0x00 },
{ WCD9335_CDC_TX4_TX_PATH_192_CFG , 0x00 },
{ WCD9335_CDC_TX4_TX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_TX4_TX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_TX4_TX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_TX4_TX_PATH_SEC3 , 0x0c },
{ WCD9335_CDC_TX4_TX_PATH_SEC4 , 0x20 },
{ WCD9335_CDC_TX4_TX_PATH_SEC5 , 0x00 },
{ WCD9335_CDC_TX4_TX_PATH_SEC6 , 0x00 },
{ WCD9335_CDC_TX5_TX_PATH_CTL , 0x04 },
{ WCD9335_CDC_TX5_TX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_TX5_TX_PATH_CFG1 , 0x00 },
{ WCD9335_CDC_TX5_TX_VOL_CTL , 0x00 },
{ WCD9335_CDC_TX5_TX_PATH_192_CTL , 0x00 },
{ WCD9335_CDC_TX5_TX_PATH_192_CFG , 0x00 },
{ WCD9335_CDC_TX5_TX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_TX5_TX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_TX5_TX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_TX5_TX_PATH_SEC3 , 0x0c },
{ WCD9335_CDC_TX5_TX_PATH_SEC4 , 0x20 },
{ WCD9335_CDC_TX5_TX_PATH_SEC5 , 0x00 },
{ WCD9335_CDC_TX5_TX_PATH_SEC6 , 0x00 },
{ WCD9335_CDC_TX6_TX_PATH_CTL , 0x04 },
{ WCD9335_CDC_TX6_TX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_TX6_TX_PATH_CFG1 , 0x00 },
{ WCD9335_CDC_TX6_TX_VOL_CTL , 0x00 },
{ WCD9335_CDC_TX6_TX_PATH_192_CTL , 0x00 },
{ WCD9335_CDC_TX6_TX_PATH_192_CFG , 0x00 },
{ WCD9335_CDC_TX6_TX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_TX6_TX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_TX6_TX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_TX6_TX_PATH_SEC3 , 0x0c },
{ WCD9335_CDC_TX6_TX_PATH_SEC4 , 0x20 },
{ WCD9335_CDC_TX6_TX_PATH_SEC5 , 0x00 },
{ WCD9335_CDC_TX6_TX_PATH_SEC6 , 0x00 },
{ WCD9335_CDC_TX7_TX_PATH_CTL , 0x04 },
{ WCD9335_CDC_TX7_TX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_TX7_TX_PATH_CFG1 , 0x00 },
{ WCD9335_CDC_TX7_TX_VOL_CTL , 0x00 },
{ WCD9335_CDC_TX7_TX_PATH_192_CTL , 0x00 },
{ WCD9335_CDC_TX7_TX_PATH_192_CFG , 0x00 },
{ WCD9335_CDC_TX7_TX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_TX7_TX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_TX7_TX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_TX7_TX_PATH_SEC3 , 0x0c },
{ WCD9335_CDC_TX7_TX_PATH_SEC4 , 0x20 },
{ WCD9335_CDC_TX7_TX_PATH_SEC5 , 0x00 },
{ WCD9335_CDC_TX7_TX_PATH_SEC6 , 0x00 },
{ WCD9335_CDC_TX8_TX_PATH_CTL , 0x04 },
{ WCD9335_CDC_TX8_TX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_TX8_TX_PATH_CFG1 , 0x00 },
{ WCD9335_CDC_TX8_TX_VOL_CTL , 0x00 },
{ WCD9335_CDC_TX8_TX_PATH_192_CTL , 0x00 },
{ WCD9335_CDC_TX8_TX_PATH_192_CFG , 0x00 },
{ WCD9335_CDC_TX8_TX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_TX8_TX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_TX8_TX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_TX8_TX_PATH_SEC3 , 0x0c },
{ WCD9335_CDC_TX8_TX_PATH_SEC4 , 0x20 },
{ WCD9335_CDC_TX8_TX_PATH_SEC5 , 0x00 },
{ WCD9335_CDC_TX8_TX_PATH_SEC6 , 0x00 },
@ -826,7 +1035,6 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_CDC_COMPANDER1_CTL4 , 0xff },
{ WCD9335_CDC_COMPANDER1_CTL5 , 0x00 },
{ WCD9335_CDC_COMPANDER1_CTL6 , 0x01 },
{ WCD9335_CDC_COMPANDER1_CTL7 , 0x0c },
{ WCD9335_CDC_COMPANDER2_CTL0 , 0x60 },
{ WCD9335_CDC_COMPANDER2_CTL1 , 0xdb },
{ WCD9335_CDC_COMPANDER2_CTL2 , 0xff },
@ -834,7 +1042,6 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_CDC_COMPANDER2_CTL4 , 0xff },
{ WCD9335_CDC_COMPANDER2_CTL5 , 0x00 },
{ WCD9335_CDC_COMPANDER2_CTL6 , 0x01 },
{ WCD9335_CDC_COMPANDER2_CTL7 , 0x0c },
{ WCD9335_CDC_COMPANDER3_CTL0 , 0x60 },
{ WCD9335_CDC_COMPANDER3_CTL1 , 0xdb },
{ WCD9335_CDC_COMPANDER3_CTL2 , 0xff },
@ -842,7 +1049,6 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_CDC_COMPANDER3_CTL4 , 0xff },
{ WCD9335_CDC_COMPANDER3_CTL5 , 0x00 },
{ WCD9335_CDC_COMPANDER3_CTL6 , 0x01 },
{ WCD9335_CDC_COMPANDER3_CTL7 , 0x0c },
{ WCD9335_CDC_COMPANDER4_CTL0 , 0x60 },
{ WCD9335_CDC_COMPANDER4_CTL1 , 0xdb },
{ WCD9335_CDC_COMPANDER4_CTL2 , 0xff },
@ -850,7 +1056,6 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_CDC_COMPANDER4_CTL4 , 0xff },
{ WCD9335_CDC_COMPANDER4_CTL5 , 0x00 },
{ WCD9335_CDC_COMPANDER4_CTL6 , 0x01 },
{ WCD9335_CDC_COMPANDER4_CTL7 , 0x0c },
{ WCD9335_CDC_COMPANDER5_CTL0 , 0x60 },
{ WCD9335_CDC_COMPANDER5_CTL1 , 0xdb },
{ WCD9335_CDC_COMPANDER5_CTL2 , 0xff },
@ -858,7 +1063,6 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_CDC_COMPANDER5_CTL4 , 0xff },
{ WCD9335_CDC_COMPANDER5_CTL5 , 0x00 },
{ WCD9335_CDC_COMPANDER5_CTL6 , 0x01 },
{ WCD9335_CDC_COMPANDER5_CTL7 , 0x0c },
{ WCD9335_CDC_COMPANDER6_CTL0 , 0x60 },
{ WCD9335_CDC_COMPANDER6_CTL1 , 0xdb },
{ WCD9335_CDC_COMPANDER6_CTL2 , 0xff },
@ -866,7 +1070,6 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_CDC_COMPANDER6_CTL4 , 0xff },
{ WCD9335_CDC_COMPANDER6_CTL5 , 0x00 },
{ WCD9335_CDC_COMPANDER6_CTL6 , 0x01 },
{ WCD9335_CDC_COMPANDER6_CTL7 , 0x0c },
{ WCD9335_CDC_COMPANDER7_CTL0 , 0x60 },
{ WCD9335_CDC_COMPANDER7_CTL1 , 0xdb },
{ WCD9335_CDC_COMPANDER7_CTL2 , 0xff },
@ -874,7 +1077,6 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_CDC_COMPANDER7_CTL4 , 0xff },
{ WCD9335_CDC_COMPANDER7_CTL5 , 0x00 },
{ WCD9335_CDC_COMPANDER7_CTL6 , 0x01 },
{ WCD9335_CDC_COMPANDER7_CTL7 , 0x0c },
{ WCD9335_CDC_COMPANDER8_CTL0 , 0x60 },
{ WCD9335_CDC_COMPANDER8_CTL1 , 0xdb },
{ WCD9335_CDC_COMPANDER8_CTL2 , 0xff },
@ -882,161 +1084,115 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_CDC_COMPANDER8_CTL4 , 0xff },
{ WCD9335_CDC_COMPANDER8_CTL5 , 0x00 },
{ WCD9335_CDC_COMPANDER8_CTL6 , 0x01 },
{ WCD9335_CDC_COMPANDER8_CTL7 , 0x0c },
{ WCD9335_CDC_RX0_RX_PATH_CTL , 0x04 },
{ WCD9335_CDC_RX0_RX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_RX0_RX_PATH_CFG1 , 0x04 },
{ WCD9335_CDC_RX0_RX_PATH_CFG2 , 0x8f },
{ WCD9335_CDC_RX0_RX_VOL_CTL , 0x00 },
{ WCD9335_CDC_RX0_RX_PATH_MIX_CTL , 0x04 },
{ WCD9335_CDC_RX0_RX_PATH_MIX_CFG , 0x0e },
{ WCD9335_CDC_RX0_RX_VOL_MIX_CTL , 0x00 },
{ WCD9335_CDC_RX0_RX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_RX0_RX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_RX0_RX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_RX0_RX_PATH_SEC3 , 0x00 },
{ WCD9335_CDC_RX0_RX_PATH_SEC5 , 0x00 },
{ WCD9335_CDC_RX0_RX_PATH_SEC6 , 0x00 },
{ WCD9335_CDC_RX0_RX_PATH_SEC7 , 0x00 },
{ WCD9335_CDC_RX0_RX_PATH_MIX_SEC0 , 0x00 },
{ WCD9335_CDC_RX0_RX_PATH_MIX_SEC1 , 0x00 },
{ WCD9335_CDC_RX1_RX_PATH_CTL , 0x04 },
{ WCD9335_CDC_RX1_RX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_RX1_RX_PATH_CFG1 , 0x04 },
{ WCD9335_CDC_RX1_RX_PATH_CFG2 , 0x8f },
{ WCD9335_CDC_RX1_RX_VOL_CTL , 0x00 },
{ WCD9335_CDC_RX1_RX_PATH_MIX_CTL , 0x04 },
{ WCD9335_CDC_RX1_RX_PATH_MIX_CFG , 0x0e },
{ WCD9335_CDC_RX1_RX_VOL_MIX_CTL , 0x00 },
{ WCD9335_CDC_RX1_RX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_RX1_RX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_RX1_RX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_RX1_RX_PATH_SEC3 , 0x00 },
{ WCD9335_CDC_RX1_RX_PATH_SEC4 , 0x00 },
{ WCD9335_CDC_RX1_RX_PATH_SEC5 , 0x00 },
{ WCD9335_CDC_RX1_RX_PATH_SEC6 , 0x00 },
{ WCD9335_CDC_RX1_RX_PATH_SEC7 , 0x00 },
{ WCD9335_CDC_RX1_RX_PATH_MIX_SEC0 , 0x00 },
{ WCD9335_CDC_RX1_RX_PATH_MIX_SEC1 , 0x00 },
{ WCD9335_CDC_RX2_RX_PATH_CTL , 0x04 },
{ WCD9335_CDC_RX2_RX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_RX2_RX_PATH_CFG1 , 0x04 },
{ WCD9335_CDC_RX2_RX_PATH_CFG2 , 0x8f },
{ WCD9335_CDC_RX2_RX_VOL_CTL , 0x00 },
{ WCD9335_CDC_RX2_RX_PATH_MIX_CTL , 0x04 },
{ WCD9335_CDC_RX2_RX_PATH_MIX_CFG , 0x0e },
{ WCD9335_CDC_RX2_RX_VOL_MIX_CTL , 0x00 },
{ WCD9335_CDC_RX2_RX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_RX2_RX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_RX2_RX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_RX2_RX_PATH_SEC3 , 0x00 },
{ WCD9335_CDC_RX2_RX_PATH_SEC4 , 0x00 },
{ WCD9335_CDC_RX2_RX_PATH_SEC5 , 0x00 },
{ WCD9335_CDC_RX2_RX_PATH_SEC6 , 0x00 },
{ WCD9335_CDC_RX2_RX_PATH_SEC7 , 0x00 },
{ WCD9335_CDC_RX2_RX_PATH_MIX_SEC0 , 0x00 },
{ WCD9335_CDC_RX2_RX_PATH_MIX_SEC1 , 0x00 },
{ WCD9335_CDC_RX3_RX_PATH_CTL , 0x04 },
{ WCD9335_CDC_RX3_RX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_RX3_RX_PATH_CFG1 , 0x04 },
{ WCD9335_CDC_RX3_RX_PATH_CFG2 , 0x8f },
{ WCD9335_CDC_RX3_RX_VOL_CTL , 0x00 },
{ WCD9335_CDC_RX3_RX_PATH_MIX_CTL , 0x04 },
{ WCD9335_CDC_RX3_RX_PATH_MIX_CFG , 0x0e },
{ WCD9335_CDC_RX3_RX_VOL_MIX_CTL , 0x00 },
{ WCD9335_CDC_RX3_RX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_RX3_RX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_RX3_RX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_RX3_RX_PATH_SEC3 , 0x00 },
{ WCD9335_CDC_RX3_RX_PATH_SEC5 , 0x00 },
{ WCD9335_CDC_RX3_RX_PATH_SEC6 , 0x00 },
{ WCD9335_CDC_RX3_RX_PATH_SEC7 , 0x00 },
{ WCD9335_CDC_RX3_RX_PATH_MIX_SEC0 , 0x00 },
{ WCD9335_CDC_RX3_RX_PATH_MIX_SEC1 , 0x00 },
{ WCD9335_CDC_RX4_RX_PATH_CTL , 0x04 },
{ WCD9335_CDC_RX4_RX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_RX4_RX_PATH_CFG1 , 0x04 },
{ WCD9335_CDC_RX4_RX_PATH_CFG2 , 0x8f },
{ WCD9335_CDC_RX4_RX_VOL_CTL , 0x00 },
{ WCD9335_CDC_RX4_RX_PATH_MIX_CTL , 0x04 },
{ WCD9335_CDC_RX4_RX_PATH_MIX_CFG , 0x0e },
{ WCD9335_CDC_RX4_RX_VOL_MIX_CTL , 0x00 },
{ WCD9335_CDC_RX4_RX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_RX4_RX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_RX4_RX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_RX4_RX_PATH_SEC3 , 0x00 },
{ WCD9335_CDC_RX4_RX_PATH_SEC5 , 0x00 },
{ WCD9335_CDC_RX4_RX_PATH_SEC6 , 0x00 },
{ WCD9335_CDC_RX4_RX_PATH_SEC7 , 0x00 },
{ WCD9335_CDC_RX4_RX_PATH_MIX_SEC0 , 0x00 },
{ WCD9335_CDC_RX4_RX_PATH_MIX_SEC1 , 0x00 },
{ WCD9335_CDC_RX5_RX_PATH_CTL , 0x04 },
{ WCD9335_CDC_RX5_RX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_RX5_RX_PATH_CFG1 , 0x04 },
{ WCD9335_CDC_RX5_RX_PATH_CFG2 , 0x8f },
{ WCD9335_CDC_RX5_RX_VOL_CTL , 0x00 },
{ WCD9335_CDC_RX5_RX_PATH_MIX_CTL , 0x04 },
{ WCD9335_CDC_RX5_RX_PATH_MIX_CFG , 0x0e },
{ WCD9335_CDC_RX5_RX_VOL_MIX_CTL , 0x00 },
{ WCD9335_CDC_RX5_RX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_RX5_RX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_RX5_RX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_RX5_RX_PATH_SEC3 , 0x00 },
{ WCD9335_CDC_RX5_RX_PATH_SEC5 , 0x00 },
{ WCD9335_CDC_RX5_RX_PATH_SEC6 , 0x00 },
{ WCD9335_CDC_RX5_RX_PATH_SEC7 , 0x00 },
{ WCD9335_CDC_RX5_RX_PATH_MIX_SEC0 , 0x00 },
{ WCD9335_CDC_RX5_RX_PATH_MIX_SEC1 , 0x00 },
{ WCD9335_CDC_RX6_RX_PATH_CTL , 0x04 },
{ WCD9335_CDC_RX6_RX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_RX6_RX_PATH_CFG1 , 0x04 },
{ WCD9335_CDC_RX6_RX_PATH_CFG2 , 0x8f },
{ WCD9335_CDC_RX6_RX_VOL_CTL , 0x00 },
{ WCD9335_CDC_RX6_RX_PATH_MIX_CTL , 0x04 },
{ WCD9335_CDC_RX6_RX_PATH_MIX_CFG , 0x0e },
{ WCD9335_CDC_RX6_RX_VOL_MIX_CTL , 0x00 },
{ WCD9335_CDC_RX6_RX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_RX6_RX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_RX6_RX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_RX6_RX_PATH_SEC3 , 0x00 },
{ WCD9335_CDC_RX6_RX_PATH_SEC5 , 0x00 },
{ WCD9335_CDC_RX6_RX_PATH_SEC6 , 0x00 },
{ WCD9335_CDC_RX6_RX_PATH_SEC7 , 0x00 },
{ WCD9335_CDC_RX6_RX_PATH_MIX_SEC0 , 0x00 },
{ WCD9335_CDC_RX6_RX_PATH_MIX_SEC1 , 0x00 },
{ WCD9335_CDC_RX7_RX_PATH_CTL , 0x04 },
{ WCD9335_CDC_RX7_RX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_RX7_RX_PATH_CFG1 , 0x04 },
{ WCD9335_CDC_RX7_RX_PATH_CFG2 , 0x8f },
{ WCD9335_CDC_RX7_RX_VOL_CTL , 0x00 },
{ WCD9335_CDC_RX7_RX_PATH_MIX_CTL , 0x04 },
{ WCD9335_CDC_RX7_RX_PATH_MIX_CFG , 0x0e },
{ WCD9335_CDC_RX7_RX_VOL_MIX_CTL , 0x00 },
{ WCD9335_CDC_RX7_RX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_RX7_RX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_RX7_RX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_RX7_RX_PATH_SEC3 , 0x00 },
{ WCD9335_CDC_RX7_RX_PATH_SEC5 , 0x00 },
{ WCD9335_CDC_RX7_RX_PATH_SEC6 , 0x00 },
{ WCD9335_CDC_RX7_RX_PATH_SEC7 , 0x00 },
{ WCD9335_CDC_RX7_RX_PATH_MIX_SEC0 , 0x00 },
{ WCD9335_CDC_RX7_RX_PATH_MIX_SEC1 , 0x00 },
{ WCD9335_CDC_RX8_RX_PATH_CTL , 0x04 },
{ WCD9335_CDC_RX8_RX_PATH_CFG0 , 0x00 },
{ WCD9335_CDC_RX8_RX_PATH_CFG1 , 0x04 },
{ WCD9335_CDC_RX8_RX_PATH_CFG2 , 0x8f },
{ WCD9335_CDC_RX8_RX_VOL_CTL , 0x00 },
{ WCD9335_CDC_RX8_RX_PATH_MIX_CTL , 0x04 },
{ WCD9335_CDC_RX8_RX_PATH_MIX_CFG , 0x0e },
{ WCD9335_CDC_RX8_RX_VOL_MIX_CTL , 0x00 },
{ WCD9335_CDC_RX8_RX_PATH_SEC0 , 0x00 },
{ WCD9335_CDC_RX8_RX_PATH_SEC1 , 0x00 },
{ WCD9335_CDC_RX8_RX_PATH_SEC2 , 0x00 },
{ WCD9335_CDC_RX8_RX_PATH_SEC3 , 0x00 },
{ WCD9335_CDC_RX8_RX_PATH_SEC5 , 0x00 },
{ WCD9335_CDC_RX8_RX_PATH_SEC6 , 0x00 },
{ WCD9335_CDC_RX8_RX_PATH_SEC7 , 0x00 },
{ WCD9335_CDC_RX8_RX_PATH_MIX_SEC0 , 0x00 },
{ WCD9335_CDC_RX8_RX_PATH_MIX_SEC1 , 0x00 },
/* Page #12 registers */
{ WCD9335_PAGE12_PAGE_REGISTER , 0x00 },
@ -1104,10 +1260,6 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_CDC_VBAT_VBAT_DEBUG1 , 0x00 },
{ WCD9335_CDC_VBAT_VBAT_GAIN_UPD_MON , 0x00 },
{ WCD9335_CDC_VBAT_VBAT_GAIN_MON_VAL , 0x00 },
{ WCD9335_SPLINE_SRC0_CLK_RST_CTL_0 , 0x00 },
{ WCD9335_SPLINE_SRC1_CLK_RST_CTL_0 , 0x00 },
{ WCD9335_SPLINE_SRC2_CLK_RST_CTL_0 , 0x00 },
{ WCD9335_SPLINE_SRC3_CLK_RST_CTL_0 , 0x00 },
{ WCD9335_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL , 0x04 },
{ WCD9335_CDC_SIDETONE_SRC0_ST_SRC_PATH_CFG1 , 0x00 },
{ WCD9335_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL , 0x04 },
@ -1171,7 +1323,6 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2 , 0x00 },
{ WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3 , 0x00 },
{ WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL , 0x00 },
{ WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL , 0x00 },
{ WCD9335_CDC_CLK_RST_CTRL_SWR_CONTROL , 0x00 },
{ WCD9335_CDC_PROX_DETECT_PROX_CTL , 0x08 },
{ WCD9335_CDC_PROX_DETECT_PROX_POLL_PERIOD0 , 0x00 },
@ -1278,8 +1429,6 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_TEST_DEBUG_PIN_CTL_DATA_3 , 0x00 },
{ WCD9335_TEST_DEBUG_PAD_DRVCTL , 0x00 },
{ WCD9335_TEST_DEBUG_PIN_STATUS , 0x00 },
{ WCD9335_TEST_DEBUG_NPL_DLY_TEST_1 , 0x00 },
{ WCD9335_TEST_DEBUG_NPL_DLY_TEST_2 , 0x00 },
{ WCD9335_TEST_DEBUG_MEM_CTRL , 0x00 },
{ WCD9335_TEST_DEBUG_DEBUG_BUS_SEL , 0x00 },
{ WCD9335_TEST_DEBUG_DEBUG_JTAG , 0x00 },
@ -1288,6 +1437,49 @@ static const struct reg_default wcd9335_defaults[] = {
{ WCD9335_TEST_DEBUG_DEBUG_EN_3 , 0x00 },
};
/*
* wcd9335_regmap_register_patch: Update register defaults based on version
* @regmap: handle to wcd9xxx regmap
* @version: wcd9335 version
*
* Returns error code in case of failure or 0 for success
*/
int wcd9335_regmap_register_patch(struct regmap *regmap, int version)
{
int rc;
int i;
if (!regmap) {
pr_err("%s: regmap struct is NULL\n", __func__);
return -EINVAL;
}
switch (version) {
case TASHA_VERSION_1_0:
case TASHA_VERSION_1_1:
regcache_cache_only(regmap, true);
for (i = 0; i < ARRAY_SIZE(wcd9335_1_x_defaults); i++)
rc = regmap_write(regmap, wcd9335_1_x_defaults[i].reg,
wcd9335_1_x_defaults[i].def);
regcache_cache_only(regmap, false);
break;
case TASHA_VERSION_2_0:
regcache_cache_only(regmap, true);
for (i = 0; i < ARRAY_SIZE(wcd9335_2_0_defaults); i++)
rc = regmap_write(regmap, wcd9335_2_0_defaults[i].reg,
wcd9335_2_0_defaults[i].def);
regcache_cache_only(regmap, false);
break;
default:
pr_err("%s: unknown version: %d\n", __func__, version);
rc = -EINVAL;
break;
}
return rc;
}
EXPORT_SYMBOL(wcd9335_regmap_register_patch);
static bool wcd9335_is_readable_register(struct device *dev, unsigned int reg)
{
u8 pg_num, reg_offset;
@ -1381,6 +1573,12 @@ static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg)
case WCD9335_VBADC_ADC_DOUTMSB:
case WCD9335_VBADC_ADC_DOUTLSB:
case WCD9335_CDC_VBAT_VBAT_GAIN_MON_VAL:
case WCD9335_DATA_HUB_NATIVE_FIFO_STATUS:
case WCD9335_MBHC_FSM_STATUS:
case WCD9335_SPLINE_SRC0_STATUS:
case WCD9335_SPLINE_SRC1_STATUS:
case WCD9335_SPLINE_SRC2_STATUS:
case WCD9335_SPLINE_SRC3_STATUS:
return true;
default:
return false;

11
drivers/mfd/wcd9335-tables.c
View File

@ -105,6 +105,8 @@ const u8 wcd9335_page0_reg_readable[WCD9335_PAGE_SIZE] = {
[WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD0_R_CFG)] = 1,
[WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD1_L_CFG)] = 1,
[WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD1_R_CFG)] = 1,
[WCD9335_REG(WCD9335_DATA_HUB_NATIVE_FIFO_SYNC)] = 1,
[WCD9335_REG(WCD9335_DATA_HUB_NATIVE_FIFO_STATUS)] = 1,
[WCD9335_REG(WCD9335_INTR_CFG)] = 1,
[WCD9335_REG(WCD9335_INTR_CLR_COMMIT)] = 0,
[WCD9335_REG(WCD9335_INTR_PIN1_MASK0)] = 1,
@ -366,10 +368,13 @@ const u8 wcd9335_page2_reg_readable[WCD9335_PAGE_SIZE] = {
[WCD9335_REG(WCD9335_CPE_SS_US_EC_MUX_CFG)] = 1,
[WCD9335_REG(WCD9335_CPE_SS_MAD_CTL)] = 1,
[WCD9335_REG(WCD9335_CPE_SS_CPAR_CTL)] = 1,
[WCD9335_REG(WCD9335_CPE_SS_TX_PP_BUF_INT_PERIOD)] = 1,
[WCD9335_REG(WCD9335_CPE_SS_TX_PP_CFG)] = 1,
[WCD9335_REG(WCD9335_CPE_SS_DMIC0_CTL)] = 1,
[WCD9335_REG(WCD9335_CPE_SS_DMIC1_CTL)] = 1,
[WCD9335_REG(WCD9335_CPE_SS_DMIC2_CTL)] = 1,
[WCD9335_REG(WCD9335_CPE_SS_DMIC_CFG)] = 1,
[WCD9335_REG(WCD9335_CPE_SS_SVA_CFG)] = 1,
[WCD9335_REG(WCD9335_CPE_SS_CPAR_CFG)] = 1,
[WCD9335_REG(WCD9335_CPE_SS_WDOG_CFG)] = 1,
[WCD9335_REG(WCD9335_CPE_SS_BACKUP_INT)] = 0,
@ -710,6 +715,7 @@ const u8 wcd9335_page10_reg_readable[WCD9335_PAGE_SIZE] = {
[WCD9335_REG(WCD9335_CDC_TX0_TX_PATH_SEC4)] = 1,
[WCD9335_REG(WCD9335_CDC_TX0_TX_PATH_SEC5)] = 1,
[WCD9335_REG(WCD9335_CDC_TX0_TX_PATH_SEC6)] = 1,
[WCD9335_REG(WCD9335_CDC_TX0_TX_PATH_SEC7)] = 1,
[WCD9335_REG(WCD9335_CDC_TX1_TX_PATH_CTL)] = 1,
[WCD9335_REG(WCD9335_CDC_TX1_TX_PATH_CFG0)] = 1,
[WCD9335_REG(WCD9335_CDC_TX1_TX_PATH_CFG1)] = 1,
@ -1114,9 +1120,13 @@ const u8 wcd9335_page12_reg_readable[WCD9335_PAGE_SIZE] = {
[WCD9335_REG(WCD9335_CDC_VBAT_VBAT_GAIN_UPD_MON)] = 0,
[WCD9335_REG(WCD9335_CDC_VBAT_VBAT_GAIN_MON_VAL)] = 1,
[WCD9335_REG(WCD9335_SPLINE_SRC0_CLK_RST_CTL_0)] = 1,
[WCD9335_REG(WCD9335_SPLINE_SRC0_STATUS)] = 1,
[WCD9335_REG(WCD9335_SPLINE_SRC1_CLK_RST_CTL_0)] = 1,
[WCD9335_REG(WCD9335_SPLINE_SRC1_STATUS)] = 1,
[WCD9335_REG(WCD9335_SPLINE_SRC2_CLK_RST_CTL_0)] = 1,
[WCD9335_REG(WCD9335_SPLINE_SRC2_STATUS)] = 1,
[WCD9335_REG(WCD9335_SPLINE_SRC3_CLK_RST_CTL_0)] = 1,
[WCD9335_REG(WCD9335_SPLINE_SRC3_STATUS)] = 1,
[WCD9335_REG(WCD9335_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL)] = 1,
[WCD9335_REG(WCD9335_CDC_SIDETONE_SRC0_ST_SRC_PATH_CFG1)] = 1,
[WCD9335_REG(WCD9335_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL)] = 1,
@ -1195,6 +1205,7 @@ const u8 wcd9335_page13_reg_readable[WCD9335_PAGE_SIZE] = {
[WCD9335_REG(WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_MSB)] = 1,
[WCD9335_REG(WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_LSB_RD)] = 1,
[WCD9335_REG(WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_MSB_RD)] = 1,
[WCD9335_REG(WCD9335_CDC_PROX_DETECT_PROX_CTL_REPEAT_PAT)] = 1,
[WCD9335_REG(WCD9335_CDC_SIDETONE_IIR0_IIR_PATH_CTL)] = 1,
[WCD9335_REG(WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL)] = 1,
[WCD9335_REG(WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL)] = 1,

55
drivers/mfd/wcd9xxx-core.c
View File

@ -945,18 +945,25 @@ static const struct wcd9xxx_codec_type wcd9xxx_codecs[] = {
ARRAY_SIZE(tasha_devs), TASHA_NUM_IRQS, -1,
WCD9XXX_SLIM_SLAVE_ADDR_TYPE_TAIKO, 0x01
},
{
TASHA2P0_MAJOR, cpu_to_le16(0x1), tasha_devs,
ARRAY_SIZE(tasha_devs), TASHA_NUM_IRQS, 2,
WCD9XXX_SLIM_SLAVE_ADDR_TYPE_TAIKO, 0x01
},
};
static void wcd9335_bring_up(struct wcd9xxx *wcd9xxx)
{
int val;
int val, byte0;
val = __wcd9xxx_reg_read(wcd9xxx,
WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0);
pr_debug("%s: codec version %s 1.0\n", __func__,
((val & 0x80) ? "greater than" : "is"));
byte0 = __wcd9xxx_reg_read(wcd9xxx,
WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0);
if (val & 0x80) {
if ((val & 0x80) && (byte0 == 0x0)) {
dev_info(wcd9xxx->dev, "%s: wcd9335 codec version is v1.1\n",
__func__);
__wcd9xxx_reg_write(wcd9xxx, WCD9335_CODEC_RPM_RST_CTL, 0x01);
__wcd9xxx_reg_write(wcd9xxx, WCD9335_SIDO_SIDO_CCL_2, 0xFC);
__wcd9xxx_reg_write(wcd9xxx, WCD9335_SIDO_SIDO_CCL_4, 0x21);
@ -967,7 +974,20 @@ static void wcd9335_bring_up(struct wcd9xxx *wcd9xxx)
__wcd9xxx_reg_write(wcd9xxx,
WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3);
__wcd9xxx_reg_write(wcd9xxx, WCD9335_CODEC_RPM_RST_CTL, 0x3);
} else if (byte0 == 0x1) {
dev_info(wcd9xxx->dev, "%s: wcd9335 codec version is v2.0\n",
__func__);
__wcd9xxx_reg_write(wcd9xxx, WCD9335_CODEC_RPM_RST_CTL, 0x01);
__wcd9xxx_reg_write(wcd9xxx,
WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5);
__wcd9xxx_reg_write(wcd9xxx,
WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7);
__wcd9xxx_reg_write(wcd9xxx,
WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3);
__wcd9xxx_reg_write(wcd9xxx, WCD9335_CODEC_RPM_RST_CTL, 0x3);
} else {
dev_info(wcd9xxx->dev, "%s: wcd9335 codec version is v1.0\n",
__func__);
__wcd9xxx_reg_write(wcd9xxx, WCD9335_CODEC_RPM_RST_CTL, 0x01);
__wcd9xxx_reg_write(wcd9xxx, WCD9335_SIDO_SIDO_CCL_2, 0xFC);
__wcd9xxx_reg_write(wcd9xxx, WCD9335_SIDO_SIDO_CCL_4, 0x21);
@ -979,16 +999,8 @@ static void wcd9335_bring_up(struct wcd9xxx *wcd9xxx)
static void wcd9335_bring_down(struct wcd9xxx *wcd9xxx)
{
int val;
val = __wcd9xxx_reg_read(wcd9xxx,
WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0);
if (val & 0x80)
__wcd9xxx_reg_write(wcd9xxx,
WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x4);
else
__wcd9xxx_reg_write(wcd9xxx,
WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7);
__wcd9xxx_reg_write(wcd9xxx,
WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x4);
}
static void wcd9xxx_bring_up(struct wcd9xxx *wcd9xxx)
@ -1368,6 +1380,7 @@ static void wcd9xxx_core_res_update_irq_regs(
{
switch (id_major) {
case TASHA_MAJOR:
case TASHA2P0_MAJOR:
core_res->intr_reg[WCD9XXX_INTR_STATUS_BASE] =
WCD9335_INTR_PIN1_STATUS0;
core_res->intr_reg[WCD9XXX_INTR_CLEAR_BASE] =
@ -1403,6 +1416,7 @@ static int wcd9xxx_device_init(struct wcd9xxx *wcd9xxx)
u8 version;
const struct wcd9xxx_codec_type *found;
struct wcd9xxx_core_resource *core_res = &wcd9xxx->core_res;
regmap_patch_fptr regmap_apply_patch = NULL;
mutex_init(&wcd9xxx->io_lock);
mutex_init(&wcd9xxx->xfer_lock);
@ -1429,7 +1443,8 @@ static int wcd9xxx_device_init(struct wcd9xxx *wcd9xxx)
} else if (wcd9xxx->codec_type->id_major == TOMTOM_MAJOR) {
core_res->intr_table = intr_tbl_v3;
core_res->intr_table_size = ARRAY_SIZE(intr_tbl_v3);
} else if (wcd9xxx->codec_type->id_major == TASHA_MAJOR) {
} else if ((wcd9xxx->codec_type->id_major == TASHA_MAJOR) ||
(wcd9xxx->codec_type->id_major == TASHA2P0_MAJOR)) {
core_res->intr_table = intr_tbl_v4;
core_res->intr_table_size = ARRAY_SIZE(intr_tbl_v4);
} else {
@ -1453,6 +1468,16 @@ static int wcd9xxx_device_init(struct wcd9xxx *wcd9xxx)
ret = wcd9xxx_regmap_init_cache(wcd9xxx);
if (ret)
goto err_irq;
regmap_apply_patch = wcd9xxx_get_regmap_reg_patch(
wcd9xxx->type);
if (regmap_apply_patch) {
ret = regmap_apply_patch(wcd9xxx->regmap,
wcd9xxx->version);
if (ret)
dev_err(wcd9xxx->dev,
"Failed to register patch: %d\n", ret);
}
}
ret = mfd_add_devices(wcd9xxx->dev, -1, found->dev, found->size,

22
drivers/mfd/wcd9xxx-regmap.h
View File

@ -17,8 +17,12 @@
#include <linux/regmap.h>
#include <linux/mfd/wcd9xxx/core.h>
typedef int (*regmap_patch_fptr)(struct regmap *, int);
#ifdef CONFIG_WCD9335_CODEC
extern struct regmap_config wcd9335_regmap_config;
extern int wcd9335_regmap_register_patch(struct regmap *regmap,
int version);
#endif
static inline struct regmap_config *wcd9xxx_get_regmap_config(int type)
@ -39,4 +43,22 @@ static inline struct regmap_config *wcd9xxx_get_regmap_config(int type)
return regmap_config;
}
static inline regmap_patch_fptr wcd9xxx_get_regmap_reg_patch(int type)
{
regmap_patch_fptr apply_patch;
switch (type) {
#ifdef CONFIG_WCD9335_CODEC
case WCD9335:
apply_patch = wcd9335_regmap_register_patch;
break;
#endif
default:
apply_patch = NULL;
break;
}
return apply_patch;
}
#endif

17
include/linux/mfd/wcd9335/registers.h
View File

@ -120,6 +120,8 @@ enum {
#define WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD0_R_CFG 0x0072
#define WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD1_L_CFG 0x0073
#define WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD1_R_CFG 0x0074
#define WCD9335_DATA_HUB_NATIVE_FIFO_SYNC 0x0075
#define WCD9335_DATA_HUB_NATIVE_FIFO_STATUS 0x007D
#define WCD9335_INTR_CFG 0x0081
#define WCD9335_INTR_CLR_COMMIT 0x0082
#define WCD9335_INTR_PIN1_MASK0 0x0089
@ -379,10 +381,13 @@ enum {
#define WCD9335_CPE_SS_US_EC_MUX_CFG 0x025e
#define WCD9335_CPE_SS_MAD_CTL 0x025f
#define WCD9335_CPE_SS_CPAR_CTL 0x0260
#define WCD9335_CPE_SS_TX_PP_BUF_INT_PERIOD 0x0261
#define WCD9335_CPE_SS_TX_PP_CFG 0x0262
#define WCD9335_CPE_SS_DMIC0_CTL 0x0263
#define WCD9335_CPE_SS_DMIC1_CTL 0x0264
#define WCD9335_CPE_SS_DMIC2_CTL 0x0265
#define WCD9335_CPE_SS_DMIC_CFG 0x0266
#define WCD9335_CPE_SS_SVA_CFG 0x0267
#define WCD9335_CPE_SS_CPAR_CFG 0x0271
#define WCD9335_CPE_SS_WDOG_CFG 0x0272
#define WCD9335_CPE_SS_BACKUP_INT 0x0273
@ -510,7 +515,8 @@ enum {
#define WCD9335_MBHC_PLUG_DETECT_CTL 0x0658
#define WCD9335_MBHC_ZDET_ANA_CTL 0x0659
#define WCD9335_MBHC_ZDET_RAMP_CTL 0x065a
#define WCD9335_MBHC_FSM_DEBUG 0x065b
#define WCD9335_MBHC_FSM_DEBUG 0x065b /* v1.x */
#define WCD9335_MBHC_FSM_STATUS 0x065b /* v2.0 */
#define WCD9335_MBHC_TEST_CTL 0x065c
#define WCD9335_VBADC_SUBBLOCK_EN 0x065d
#define WCD9335_VBADC_IBIAS_FE 0x065e
@ -596,7 +602,8 @@ enum {
#define WCD9335_FLYBACK_VNEG_DAC_CTRL_1 0x06ae
#define WCD9335_FLYBACK_VNEG_DAC_CTRL_2 0x06af
#define WCD9335_FLYBACK_VNEG_DAC_CTRL_3 0x06b0
#define WCD9335_FLYBACK_VNEG_DAC_CTRL_4 0x06b1
#define WCD9335_FLYBACK_VNEG_DAC_CTRL_4 0x06b1 /* v1.x */
#define WCD9335_FLYBACK_CTRL_1 0x06b1 /* v2.0 */
#define WCD9335_FLYBACK_TEST_CTL 0x06b2
#define WCD9335_RX_AUX_SW_CTL 0x06b3
#define WCD9335_RX_PA_AUX_IN_CONN 0x06b4
@ -721,6 +728,7 @@ enum {
#define WCD9335_CDC_TX0_TX_PATH_SEC4 0x0a3b
#define WCD9335_CDC_TX0_TX_PATH_SEC5 0x0a3c
#define WCD9335_CDC_TX0_TX_PATH_SEC6 0x0a3d
#define WCD9335_CDC_TX0_TX_PATH_SEC7 0x0a3e
#define WCD9335_CDC_TX1_TX_PATH_CTL 0x0a41
#define WCD9335_CDC_TX1_TX_PATH_CFG0 0x0a42
#define WCD9335_CDC_TX1_TX_PATH_CFG1 0x0a43
@ -1123,9 +1131,13 @@ enum {
#define WCD9335_CDC_VBAT_VBAT_GAIN_UPD_MON 0x0c50
#define WCD9335_CDC_VBAT_VBAT_GAIN_MON_VAL 0x0c51
#define WCD9335_SPLINE_SRC0_CLK_RST_CTL_0 0x0c55
#define WCD9335_SPLINE_SRC0_STATUS 0x0c56
#define WCD9335_SPLINE_SRC1_CLK_RST_CTL_0 0x0c6d
#define WCD9335_SPLINE_SRC1_STATUS 0x0c6e
#define WCD9335_SPLINE_SRC2_CLK_RST_CTL_0 0x0c85
#define WCD9335_SPLINE_SRC2_STATUS 0x0c86
#define WCD9335_SPLINE_SRC3_CLK_RST_CTL_0 0x0c9d
#define WCD9335_SPLINE_SRC3_STATUS 0x0c9e
#define WCD9335_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL 0x0cb5
#define WCD9335_CDC_SIDETONE_SRC0_ST_SRC_PATH_CFG1 0x0cb6
#define WCD9335_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL 0x0cb9
@ -1203,6 +1215,7 @@ enum {
#define WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_MSB 0x0d51
#define WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_LSB_RD 0x0d52
#define WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_MSB_RD 0x0d53
#define WCD9335_CDC_PROX_DETECT_PROX_CTL_REPEAT_PAT 0x0d54
#define WCD9335_CDC_SIDETONE_IIR0_IIR_PATH_CTL 0x0d55
#define WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL 0x0d56
#define WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL 0x0d57

4
include/linux/mfd/wcd9xxx/core.h
View File

@ -54,10 +54,13 @@
#define TASHA_VERSION_1_0 0
#define TASHA_VERSION_1_1 1
#define TASHA_VERSION_2_0 2
#define TASHA_IS_1_0(ver) \
((ver == TASHA_VERSION_1_0) ? 1 : 0)
#define TASHA_IS_1_1(ver) \
((ver == TASHA_VERSION_1_1) ? 1 : 0)
#define TASHA_IS_2_0(ver) \
((ver == TASHA_VERSION_2_0) ? 1 : 0)
enum wcd9xxx_slim_slave_addr_type {
WCD9XXX_SLIM_SLAVE_ADDR_TYPE_TABLA,
@ -221,6 +224,7 @@ enum wcd9xxx_chipid_major {
TAPAN_MAJOR = cpu_to_le16(0x103),
TOMTOM_MAJOR = cpu_to_le16(0x105),
TASHA_MAJOR = cpu_to_le16(0x0),
TASHA2P0_MAJOR = cpu_to_le16(0x107),
};
enum codec_power_states {