mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-11-07 04:09:21 +00:00
bfin: reorg clock init steps for bf609
So that user can set the clocks through menuconfig. Signed-off-by: Bob Liu <lliubbo@gmail.com>
This commit is contained in:
Bob Liu
parent
e70f466067
commit
f82f16d2f5
4 changed files with 224 additions and 133 deletions
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@ -352,6 +352,11 @@ config MEM_MT48H32M16LFCJ_75
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depends on (BFIN526_EZBRD)
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default y
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config MEM_MT47H64M16
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bool
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depends on (BFIN609_EZKIT)
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default y
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source "arch/blackfin/mach-bf518/Kconfig"
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source "arch/blackfin/mach-bf527/Kconfig"
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source "arch/blackfin/mach-bf533/Kconfig"
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@ -6,6 +6,9 @@
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* Licensed under the GPL-2 or later.
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*/
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#ifndef __MEM_INIT_H__
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#define __MEM_INIT_H__
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#if defined(EBIU_SDGCTL)
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#if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
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defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
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@ -277,3 +280,212 @@
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#else
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#define PLL_BYPASS 0
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#endif
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#ifdef CONFIG_BF60x
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/* DMC status bits */
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#define IDLE 0x1
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#define MEMINITDONE 0x4
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#define SRACK 0x8
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#define PDACK 0x10
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#define DPDACK 0x20
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#define DLLCALDONE 0x2000
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#define PENDREF 0xF0000
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#define PHYRDPHASE 0xF00000
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#define PHYRDPHASE_OFFSET 20
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/* DMC control bits */
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#define LPDDR 0x2
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#define INIT 0x4
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#define SRREQ 0x8
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#define PDREQ 0x10
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#define DPDREQ 0x20
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#define PREC 0x40
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#define ADDRMODE 0x100
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#define RDTOWR 0xE00
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#define PPREF 0x1000
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#define DLLCAL 0x2000
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/* DMC DLL control bits */
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#define DLLCALRDCNT 0xFF
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#define DATACYC 0xF00
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#define DATACYC_OFFSET 8
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/* CGU Divisor bits */
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#define CSEL_OFFSET 0
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#define S0SEL_OFFSET 5
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#define SYSSEL_OFFSET 8
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#define S1SEL_OFFSET 13
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#define DSEL_OFFSET 16
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#define OSEL_OFFSET 22
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#define ALGN 0x20000000
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#define UPDT 0x40000000
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#define LOCK 0x80000000
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/* CGU Status bits */
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#define PLLEN 0x1
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#define PLLBP 0x2
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#define PLOCK 0x4
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#define CLKSALGN 0x8
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/* CGU Control bits */
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#define MSEL_MASK 0x7F00
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#define DF_MASK 0x1
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struct ddr_config {
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u32 ddr_clk;
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u32 dmc_ddrctl;
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u32 dmc_ddrcfg;
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u32 dmc_ddrtr0;
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u32 dmc_ddrtr1;
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u32 dmc_ddrtr2;
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u32 dmc_ddrmr;
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u32 dmc_ddrmr1;
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};
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#if defined(CONFIG_MEM_MT47H64M16)
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static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = {
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[0] = {
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.ddr_clk = 125,
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.dmc_ddrctl = 0x00000904,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20705212,
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.dmc_ddrtr1 = 0x201003CF,
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.dmc_ddrtr2 = 0x00320107,
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.dmc_ddrmr = 0x00000422,
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.dmc_ddrmr1 = 0x4,
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},
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[1] = {
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.ddr_clk = 133,
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.dmc_ddrctl = 0x00000904,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20806313,
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.dmc_ddrtr1 = 0x2013040D,
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.dmc_ddrtr2 = 0x00320108,
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.dmc_ddrmr = 0x00000632,
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.dmc_ddrmr1 = 0x4,
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},
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[2] = {
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.ddr_clk = 150,
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.dmc_ddrctl = 0x00000904,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20A07323,
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.dmc_ddrtr1 = 0x20160492,
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.dmc_ddrtr2 = 0x00320209,
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.dmc_ddrmr = 0x00000632,
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.dmc_ddrmr1 = 0x4,
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},
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[3] = {
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.ddr_clk = 166,
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.dmc_ddrctl = 0x00000904,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20A07323,
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.dmc_ddrtr1 = 0x2016050E,
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.dmc_ddrtr2 = 0x00320209,
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.dmc_ddrmr = 0x00000632,
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.dmc_ddrmr1 = 0x4,
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},
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[4] = {
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.ddr_clk = 200,
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.dmc_ddrctl = 0x00000904,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20a07323,
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.dmc_ddrtr1 = 0x2016050f,
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.dmc_ddrtr2 = 0x00320509,
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.dmc_ddrmr = 0x00000632,
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.dmc_ddrmr1 = 0x4,
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},
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[5] = {
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.ddr_clk = 225,
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.dmc_ddrctl = 0x00000904,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20E0A424,
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.dmc_ddrtr1 = 0x302006DB,
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.dmc_ddrtr2 = 0x0032020D,
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.dmc_ddrmr = 0x00000842,
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.dmc_ddrmr1 = 0x4,
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},
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[6] = {
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.ddr_clk = 250,
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.dmc_ddrctl = 0x00000904,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20E0A424,
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.dmc_ddrtr1 = 0x3020079E,
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.dmc_ddrtr2 = 0x0032020D,
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.dmc_ddrmr = 0x00000842,
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.dmc_ddrmr1 = 0x4,
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},
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};
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#endif
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static inline void dmc_enter_self_refresh(void)
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{
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if (bfin_read_DMC0_STAT() & MEMINITDONE) {
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bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ);
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while (!(bfin_read_DMC0_STAT() & SRACK))
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continue;
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}
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}
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static inline void dmc_exit_self_refresh(void)
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{
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if (bfin_read_DMC0_STAT() & MEMINITDONE) {
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bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ);
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while (bfin_read_DMC0_STAT() & SRACK)
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continue;
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}
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}
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static inline void init_cgu(u32 cgu_div, u32 cgu_ctl)
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{
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dmc_enter_self_refresh();
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/* Don't set the same value of MSEL and DF to CGU_CTL */
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if ((bfin_read32(CGU0_CTL) & (MSEL_MASK | DF_MASK))
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!= cgu_ctl) {
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bfin_write32(CGU0_DIV, cgu_div);
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bfin_write32(CGU0_CTL, cgu_ctl);
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while ((bfin_read32(CGU0_STAT) & (CLKSALGN | PLLBP)) ||
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!(bfin_read32(CGU0_STAT) & PLOCK))
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continue;
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}
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bfin_write32(CGU0_DIV, cgu_div | UPDT);
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while (bfin_read32(CGU0_STAT) & CLKSALGN)
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continue;
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dmc_exit_self_refresh();
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}
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static inline void init_dmc(u32 dmc_clk)
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{
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int i, dlldatacycle, dll_ctl;
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for (i = 0; i < 7; i++) {
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if (ddr_config_table[i].ddr_clk == dmc_clk) {
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bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg);
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bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0);
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bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1);
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bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
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bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
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bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
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bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
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break;
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}
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}
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while (!(bfin_read_DMC0_STAT() & MEMINITDONE))
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continue;
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dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >> PHYRDPHASE_OFFSET;
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dll_ctl = bfin_read_DMC0_DLLCTL();
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dll_ctl &= ~DATACYC;
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bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET));
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while (!(bfin_read_DMC0_STAT() & DLLCALDONE))
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continue;
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}
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#endif
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#endif /*__MEM_INIT_H__*/
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@ -2665,7 +2665,6 @@
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#define DEVSZ_1G 0x400 /* DMC External Bank Size = 1Gbit */
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#define DEVSZ_2G 0x500 /* DMC External Bank Size = 2Gbit */
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/* =========================
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L2CTL Registers
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========================= */
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@ -16,23 +16,14 @@
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#include <asm/dpmc.h>
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#ifdef CONFIG_BF60x
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#define CSEL_P 0
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#define S0SEL_P 5
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#define SYSSEL_P 8
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#define S1SEL_P 13
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#define DSEL_P 16
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#define OSEL_P 22
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#define ALGN_P 29
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#define UPDT_P 30
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#define LOCK_P 31
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#define CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CLKIN_HALF)
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#define CGU_DIV_VAL \
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((CONFIG_CCLK_DIV << CSEL_P) | \
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(CONFIG_SCLK_DIV << SYSSEL_P) | \
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(CONFIG_SCLK0_DIV << S0SEL_P) | \
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(CONFIG_SCLK1_DIV << S1SEL_P) | \
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(CONFIG_DCLK_DIV << DSEL_P))
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((CONFIG_CCLK_DIV << CSEL_OFFSET) | \
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(CONFIG_SCLK_DIV << SYSSEL_OFFSET) | \
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(CONFIG_SCLK0_DIV << S0SEL_OFFSET) | \
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(CONFIG_SCLK1_DIV << S1SEL_OFFSET) | \
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(CONFIG_DCLK_DIV << DSEL_OFFSET))
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#define CONFIG_BFIN_DCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_DCLK_DIV) / 1000000)
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#if ((CONFIG_BFIN_DCLK != 125) && \
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@ -41,89 +32,7 @@
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(CONFIG_BFIN_DCLK != 225) && (CONFIG_BFIN_DCLK != 250))
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#error "DCLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
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#endif
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struct ddr_config {
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u32 ddr_clk;
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u32 dmc_ddrctl;
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u32 dmc_ddrcfg;
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u32 dmc_ddrtr0;
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u32 dmc_ddrtr1;
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u32 dmc_ddrtr2;
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u32 dmc_ddrmr;
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u32 dmc_ddrmr1;
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};
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struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = {
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[0] = {
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.ddr_clk = 125,
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.dmc_ddrctl = 0x00000904,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20705212,
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.dmc_ddrtr1 = 0x201003CF,
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.dmc_ddrtr2 = 0x00320107,
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.dmc_ddrmr = 0x00000422,
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.dmc_ddrmr1 = 0x4,
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},
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[1] = {
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.ddr_clk = 133,
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.dmc_ddrctl = 0x00000904,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20806313,
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.dmc_ddrtr1 = 0x2013040D,
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.dmc_ddrtr2 = 0x00320108,
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.dmc_ddrmr = 0x00000632,
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.dmc_ddrmr1 = 0x4,
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},
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[2] = {
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.ddr_clk = 150,
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.dmc_ddrctl = 0x00000904,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20A07323,
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.dmc_ddrtr1 = 0x20160492,
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.dmc_ddrtr2 = 0x00320209,
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.dmc_ddrmr = 0x00000632,
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.dmc_ddrmr1 = 0x4,
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},
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[3] = {
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.ddr_clk = 166,
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.dmc_ddrctl = 0x00000904,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20A07323,
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.dmc_ddrtr1 = 0x2016050E,
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.dmc_ddrtr2 = 0x00320209,
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.dmc_ddrmr = 0x00000632,
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.dmc_ddrmr1 = 0x4,
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},
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[4] = {
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.ddr_clk = 200,
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.dmc_ddrctl = 0x00000904,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20a07323,
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.dmc_ddrtr1 = 0x2016050f,
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.dmc_ddrtr2 = 0x00320509,
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.dmc_ddrmr = 0x00000632,
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.dmc_ddrmr1 = 0x4,
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},
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[5] = {
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.ddr_clk = 225,
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.dmc_ddrctl = 0x00000904,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20E0A424,
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.dmc_ddrtr1 = 0x302006DB,
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.dmc_ddrtr2 = 0x0032020D,
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.dmc_ddrmr = 0x00000842,
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.dmc_ddrmr1 = 0x4,
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},
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[6] = {
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.ddr_clk = 250,
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.dmc_ddrctl = 0x00000904,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20E0A424,
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.dmc_ddrtr1 = 0x3020079E,
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.dmc_ddrtr2 = 0x0032020D,
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.dmc_ddrmr = 0x00000842,
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.dmc_ddrmr1 = 0x4,
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},
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};
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#else
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#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */
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#define PLL_CTL_VAL \
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@ -144,43 +53,9 @@ void init_clocks(void)
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* in the middle of reprogramming things, and that'll screw us up.
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* For example, any automatic DMAs left by U-Boot for splash screens.
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*/
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#ifdef CONFIG_BF60x
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int i, dlldatacycle, dll_ctl;
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bfin_write32(CGU0_DIV, CGU_DIV_VAL);
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bfin_write32(CGU0_CTL, CGU_CTL_VAL);
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while ((bfin_read32(CGU0_STAT) & 0x8) || !(bfin_read32(CGU0_STAT) & 0x4))
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continue;
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bfin_write32(CGU0_DIV, CGU_DIV_VAL | (1 << UPDT_P));
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while (bfin_read32(CGU0_STAT) & (1 << 3))
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continue;
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for (i = 0; i < 7; i++) {
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if (ddr_config_table[i].ddr_clk == CONFIG_BFIN_DCLK) {
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bfin_write_DDR0_CFG(ddr_config_table[i].dmc_ddrcfg);
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bfin_write_DDR0_TR0(ddr_config_table[i].dmc_ddrtr0);
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bfin_write_DDR0_TR1(ddr_config_table[i].dmc_ddrtr1);
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bfin_write_DDR0_TR2(ddr_config_table[i].dmc_ddrtr2);
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bfin_write_DDR0_MR(ddr_config_table[i].dmc_ddrmr);
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bfin_write_DDR0_EMR1(ddr_config_table[i].dmc_ddrmr1);
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bfin_write_DDR0_CTL(ddr_config_table[i].dmc_ddrctl);
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break;
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}
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}
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do_sync();
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while (!(bfin_read_DDR0_STAT() & 0x4))
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continue;
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dlldatacycle = (bfin_read_DDR0_STAT() & 0x00f00000) >> 20;
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dll_ctl = bfin_read_DDR0_DLLCTL();
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dll_ctl &= 0x0ff;
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bfin_write_DDR0_DLLCTL(dll_ctl | (dlldatacycle << 8));
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do_sync();
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while (!(bfin_read_DDR0_STAT() & 0x2000))
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continue;
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init_cgu(CGU_DIV_VAL, CGU_CTL_VAL);
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init_dmc(CONFIG_BFIN_DCLK);
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#else
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size_t i;
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for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
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