parisc: document the shadow registers
commit a83f58bcb24003b9de2364de7c829a263423ead7 upstream. Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -77,6 +77,14 @@ PSW default E value 0
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Shadow Registers used by interruption handler code
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TOC enable bit 1
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=========================================================================
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The PA-RISC architecture defines 7 registers as "shadow registers".
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Those are used in RETURN FROM INTERRUPTION AND RESTORE instruction to reduce
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the state save and restore time by eliminating the need for general register
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(GR) saves and restores in interruption handlers.
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Shadow registers are the GRs 1, 8, 9, 16, 17, 24, and 25.
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=========================================================================
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Register usage notes, originally from John Marvin, with some additional
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notes from Randolph Chung.
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