This is an initial driver for the new QPIC based NAND controller(NANDc)
that is introduced in MDM9x25. This driver has been leveraged from the
current driver msm_nand.c and is modified for the new hardware changes
in QPIC NANDc. Addition of SPS/BAM support is one of the major
hardware changes in new controller. It also supports only BCH ECC and
based on the device capabilities either 4 bit or 8 bit BCH ECC will
be used. This driver is based on the device tree architecture.
Change-Id: Ie9f782a796bd7c1506997e8eaa1e797310dc26a0
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Below you will find an updated version from the original series bunching all patches into one big patch
updating broken web addresses that are located in Documentation/*
Some of the addresses date as far far back as 1995 etc... so searching became a bit difficult,
the best way to deal with these is to use web.archive.org to locate these addresses that are outdated.
Now there are also some addresses pointing to .spec files some are located, but some(after searching
on the companies site)where still no where to be found. In this case I just changed the address
to the company site this way the users can contact the company and they can locate them for the users.
Signed-off-by: Justin P. Mattock <justinmattock@gmail.com>
Signed-off-by: Thomas Weber <weber@corscience.de>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Cc: Paulo Marques <pmarques@grupopie.com>
Cc: Randy Dunlap <rdunlap@xenotime.net>
Cc: Michael Neuling <mikey@neuling.org>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
This patch improves the performance of the ecc generation code by a
factor of 18 on an INTEL D920 CPU, a factor of 7 on MIPS and a factor of 5
on ARM (NSLU2)
Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Sahitya Tummala
Justin P. Mattock
Matt LaPlante
frans