During secure map, the scatterlist is converted into a
simple array of 1MB chunk addresses. This array is then
passed to TZ. The code which does this incorrectly
increments physical base address each time, besides
adding chunk size. Fix this.
Change-Id: I82b3b4eb3b008af14450873b8d34867df81e6ca8
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
Bit[9] and Bit[10] of an FSR register indicates the
page table format of the context bank and can be
non-zero even if there is no fault recorded into FSR.
Only first 9 bits [8:0] indicates type of fault 'at'
the time of fault. So, fix the false positive by just
checking over fault indicator bits only.
Change-Id: Id7c37d8d0b26002156ae3b829e3a11fb7a631fed
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
Now that non-secure CB faults also gets routed to secure
fault handler (when IOMMU is secure), we need to ensure
that custom fault handler also gets an access with clock
enabled. This was the BUG but no one earlier called
custom fault handler from secure fault handler and remained
uncaught. Fix it by maintaining clock until we return.
Also, ensure that only for valid FSR values we enter and
invoke custom fault handlers.
Change-Id: I9f883c96a8fc05409d5670c35c86301fab6c2f8c
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
Remove CONFIG_MSM_IOMMU_TLBINVAL_ON_MAP and the code
protected by it, since there is no known case now,
which requires a tlb invalidate during a map.
Change-Id: Ia9566dfadbb24345e4bcc66111dd0013a53e1b1c
Signed-off-by: Vinayak Menon <vinmenon@codeaurora.org>
Now that we route all non-secure CB fault also to the secure
fault handler, we want it to print debug info of iova_to_phys
for non-secure context banks. Add that debug feature in
secure fault handler.
Change-Id: Ie5a56c47d9e73d758daaf3d023774c32ac98dfe3
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
MSM IOMMU driver presently supports mapping of virtual
addresses of 32-bit long only. Because of this, 32-bit
long virtual address was okay and some mis-matches were
silent. This is harmless but still buggy. Also, for
64-bit virtual address mapping, some API needs update.
Make input virtual address always 'unsigned long' and
trunk (if necessary) based on the page table format.
Change-Id: I5d761246b0e150d9a0d22a9ae25581b5205e0594
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
iommu_map_sg is the newer, preferred API. Add a wrapper around
the existing map_range API for map_sg. Once all clients have been
successfully converted map_range can be removed.
Change-Id: Ib77c86f6b12b00b2bd83a4938465dc685faea624
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Virtual and physical memory allocators may return buffers
that are at physical addresses higher than 4GB. When
passing addresses to TZ, don't assume otherwise. Fix the
code to not truncate down to 32 bits (the assignment operation
u64 = u32 = u64 truncates down 64 bit addresses to 32 bits)
unnecessarily; perform the assignment in two discrete steps
to allow the desc.args[X] field to store the full 64 bit
address.
Change-Id: I27ee7f17dace8f9a59712f742f6f6219825c6b82
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Currently we're using dma_free_coherent to free a DMA allocation that
was allocated with dma_alloc_attrs. DMA allocation and free should
always use matching attributes. Failure to do so could result in
instabilities. Fix this by using dma_free_attrs. Also fix an erroneous
comment regarding the dma_alloc_attrs piece.
Change-Id: I99fed0d27b14895a5a9099944a25ef9ee1072614
Suggested-by: Joseph Chang <joechang@qti.qualcomm.com>
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
The size being passed to dmac_clean_range() inside
iommu_map_range is incorrect; instead of providing the
total length of all the chunks in the chunk list, we're
currently passing the length of just one chunk. Fix this
to pass in the right length.
Change-Id: Id9f4ce9be8a21da0e037da987b3e1fbd8d81dd2f
Signed-off-by: Neeti Desai <neetid@codeaurora.org>
We will soon be removing the `flags' parameter from iommu_domain_alloc
and iommu_ops.domain_init. In preparation for this, move the L2 redirect
flag to a domain attribute.
We now no longer need the extra parameter to iommu_domain_alloc which
was added in [8984b0e30df: "drivers: iommu: Add flags to
iommu_domain_alloc"] since we're changing the way L2 redirect is
configured. Remove it.
Change-Id: Ie0d15767ca08211740d22568683fae01e8123a26
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
Secure buffer mappings should be 1MB aligned. Add checks
for this.
CRs-Fixed: 755014
Change-Id: I377e7beaeb21cce9a828590bab20cc1cf41fd8c6
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
The scm_library has added support for a new secure world
interface which is more aligned to the ARMv8 SMC calling
convention. This new api support was missing for the
dump fault register dumping code.
CRs-Fixed: 749979
Change-Id: I2b6d4f65ee6a59af677dfd109976053768de2b80
Signed-off-by: Neeti Desai <neetid@codeaurora.org>
In general, we must do some cache maintenance when sharing buffers with
TZ since our caches are not shared with TZ. Specifically:
(1) If we put some data into a buffer then share it with TZ for
reading, the buffer must be flushed before sending it to TZ.
(2) If TZ puts some data in a buffer for us to read, the buffer must
be invalidated after receiving it from TZ.
In msm_iommu_sec_ptbl_map we are currently doing some cache maintenance
incorrectly. We are invalidating a buffer that we shared with TZ even
though we're not reading from the buffer. We're also flushing way more
than we need to. We're only sharing a single buffer of size
sizeof(phys_addr_t) with TZ but we're flushing the size of the IOMMU
mapping (which could be anything up to 2^sizeof(size_t)).
Remove the unnecessary invalidate and only flush the size of the buffer
being shared, nothing more.
Change-Id: I46d2d95319364d197ae530001851ab819a6eb6fa
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
unmap_range should return an error code, not just zero.
Technially the return code should be the number of bytes
unmapped but certain kernel clients spew errors because
of incorrect error handling. Until that can be filed,
return negative error codes to indicate an error.
Change-Id: Iae0b561c99edc216d3d484107be5938f3775e11d
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
The scm library has added support for a new secure world
interface that is more aligned to the ARMv8 SMC calling
convention. Use the new API while maintaining backward
compatibility.
Change-Id: Ib2a52aebf28ff4cb215d0726822411dde0c075ab
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Drivers require an API to be able to inform the secure world
that their devices have resumed from power collapse and security
settings need to be re-relaxed.
Transition existing users to the new API.
Change-Id: Ia5b49176c797ec9d6d35350ea98964203d622516
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
The device struct may be passed as NULL into the msm_detach_dev
function. Add check to prevent NULL pointer dereferencing.
Change-Id: I4123b60969358cd4ff9ad20b76257405aacc4257
Signed-off-by: Neeti Desai <neetid@codeaurora.org>
cache_line_size() may not be a static number for every
architecture but dynamically calculated size. Instead
use higher alignment of PAGE_SIZE for temporary
allocations.
Change-Id: Ib8a730a7f5eca650a5a98f20532ffeaa3b647491
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
Due to a hardware bug the TLB has to be invalidated
during map and map_range operations. Newer targets
no longer see this issue. Add config option
to invalidate the TLB only for older targets.
Change-Id: I5bbe84e9dde23bcf960cf5409eed41c6cea41c16
Signed-off-by: Neeti Desai <neetid@codeaurora.org>
In some architectures (at least observed on
Cortex-A53), CPU cache invalidation is not just pure
invalidation but clean + invalidation. If the cache
lines are *dirty*, then first clean will happen and DDR
gets updated with cached content and then invalidation
will be performed.
According to the above specification, we cannot just
handover buffer to non-Linux entity before cleaning its
CPU cache lines. Because, later invalidation will
overwrite the DDR content written by non-Linux.
Fix this by doing clean with proper range.
Change-Id: I8b3c6d13961e9e966a2241d5372584f59bdfbcf0
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
Present debug log mechanism of secure context bank fault
handler doesn't behave well when it tries to obtain
register dumps from secure environment and fails to get a
sane response.
It is observed that the secure environment doesn't fill up
the register dump structure passed by the kernel correctly.
This leads to secure fault handler constantly dumping
default initialized values for these register making no
sense.
This patch intends to address this issue and fixes
following.
* initialize dump holding structure and response variable
to 0
* return IRQ_NONE and do not proceed if secure
environment response is 0 length
* replace incorrect CB register address prints by
actual context numbers and register offsets.
Change-Id: I07f329fd5dcb4fc56f7bb9a6dc182b73b806005c
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
Present logic of enabling aggregated CB interrupts works only
for non-secure SMMUs. Improvise that logic to enable interrupts
for secure SMMUs also.
Change-Id: I77f914de760562ce30b7ade512a12639eb84af6d
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
Linux allocates memory for secure page tables which is passed to the secure
world. This memory is later protected from reads/writes from Linux. Using
kmalloc for this memory may allow speculative accesses to occur to
secured memory. Avoid speculative faults by using dma_alloc_coherent
with the NO_KERNEL_MAPPING attribute to avoid a non-secure mapping.
Change-Id: I3fcd82b2a1e5b82442641961c70306560ee778d8
CRs-Fixed: 621723
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Header files are no longer allowed in the directory
arch/arm/mach-msm/include/mach/ .
Move the iommu related header files to a more suitable place.
Change-Id: Ib7bbce1485d6185f669935b507040cac75368985
Signed-off-by: Larry Bassel <lbassel@codeaurora.org>
The file mach/msm_bus.h should not be included,
instead the file linux/msm-bus.h should be.
Also remove an unneeded include.
Change-Id: I6e060739977f8604409f660c72c9a983eaddfa45
Signed-off-by: Larry Bassel <lbassel@codeaurora.org>
VFE SMMU needs to be secure for new secure camera use
cases. Change the VFE to be secure and designate the
last context bank (CB) as secure. Also ensure backwards
compatability so that when running with old secure environment
we fall back to VFE SMMU being non-secure.
Change-Id: I25f31b0350ef0c1b16ebb0db531cc0e6bc556fcf
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
If we get back a partial register dump from TZ we should go ahead and
print as much as we can, rather than bailing out and not printing
anything.
Change-Id: Idcc8b14a76bf1f23bdf00b52879b3ce0ca9afdcc
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
Add support for dumping registers from the global register space. Dump
CBAR_N and CBFRSYNRA_N.
Change-Id: If20605968fac75ad791d4e63e4d089ecaf8f7ebd
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
Currently in the secure register dump code, we try to determine the
register in question by doing some reverse arithmetic on the full
address that TZ returns and matching that against known register
offsets. However, support was recently added for storing the base
physical address of the Iommu in `struct msm_iommu_drvdata'. Simplify
the code by calculating the offset of the registers being returned by TZ
by subtracting their values from the base address of the Iommu.
Change-Id: Icd6e4a35a48b808b0523ab4971cb9fb5b00125f5
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
TZ expects the physical address of the destination dump buffer to be
32-bits, even on LPAE targets. Always send a 32-bit integer. This
requires truncating the top 4 bytes of a 64-bit physical address, but
this shouldn't be a problem on current targets since all physical
addresses should be <4GB.
Change-Id: I486ed39e132be46ebfc80335024cb8d31d7ac1c2
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
There's no need to have cache wrappers anymore.
Call the appropriate cache API directly.
Change-Id: If31002ef8b3a6598700c2c59ca9a5cc19a188da6
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Implementation defined registers are now shifted to BFB registers
data. So, remove additional register writes to them.
Change-Id: Ic53c8c9c605aded616ffdc15b0b596105890a25d
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
The non secure registers in IOMMU are programmed when
CONFIG_IOMMU_NON_SECURE is enabled. The programming of these registers
is no longer dependent on this config, but depends on a check to see
if the secure environment is available.
CONFIG_IOMMU_NON_SECURE is now only used to force all SMMUs to be
programmed by the Linux kernel SMMU driver for debugging purposes.
Change-Id: I367f92fd6e5198395b83e6ca8acde66b1b012620
Signed-off-by: Neeti Desai <neetid@codeaurora.org>
Architectural changes in the ARM Linux kernel tree mandate
the eventual removal of the mach-* directories. Move the
scm driver to drivers/soc/qcom and the scm header to
include/soc/qcom to support that removal.
Change-Id: Ie660d0566de35045c1ba73fcddeda99efacf057e
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Secure page tables for SMMUs only look up for SMMUv1. Support
SMMUv2 also.
Change-Id: I802b7e3b8da8311c8f501ea939f66bd48f5649fd
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
In some cases, the secure world needs a hint as to the maximum
amount of memory that will ever be mapped. This is necessary to
optimize data structures in the secure world. Add a call to the
secure world to indicate the maximum mapped size.
Change-Id: I8d07ec2288e37057ff96777c96ed0680f75185f3
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Rename properties and compatible strings to return to the old
naming convention.
Change-Id: I90c673e150bebf26dc0882416ece6bb7c36b98b8
Signed-off-by: Kumar Gala <galak@codeaurora.org>
As we have recently moved to use 'qti' as vendor name,
reflect that change for all the code related to iommu,
including version 0 and 1.
Change-Id: If67f2a778c64fc5c49f7b07e19ec31fb0cda8d52
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
The remote spinlock was originally meant to synchronize access between
GPU and CPU accessing SMMU. However, there are more use cases that
this remote spinlock serves. This change decouples the spinlock from
GPU and adds support for taking the spinlock only for SMMUs that are
specified in the device tree.
CRs-fixed: 517873
Change-Id: Ic50992d0d1a102fbd05855e09e254e627f99ec33
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
There are several hardware private bits that are required for
proper operations of IOMMU hardware blocks. Set those bits
appropriately.
Change-Id: I60bf08dc71f7081c03ac8b271e651714b70d26c7
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Shiraz Hashim
Chintan Pandya
Vinayak Menon
Linux Build Service Account
Laura Abbott
Vikram Mulukutla
Mitchel Humpherys
Neeti Desai
Shubhraprakash Das
Neha Atri
Larry Bassel
Olav Haugan
Kumar Gala