Currently we set CONFIG_CC_OPTIMIZE_FOR_SIZE which suppressed the compiler
warning of unused variables which can lead undefined behavior e.g. memory
corruption and panic. See https://lkml.org/lkml/2013/3/25/347.
This patch fixes all the uninitilized variables in kernel
Bug: 33353384
Test: On device
Signed-off-by: Wei Wang <wvw@google.com>
Change-Id: I0ae1082f447b435d71156d471878ba71aa16c378
On certain circumstances, empty soc interrupt cannot fire even
with the proper configuration. Clearing the empty soc config
and setting it back again after a FG cycle (~1.5 seconds) is
the only way to trigger empty soc interrupt again. Add it.
While at it, remove some unused macros in the driver.
CRs-Fixed: 1003838
Change-Id: I5dda1b52e19eb2086543035e0d8d1998ce709d53
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
In case of hardware coulomb counting based capacity learning the
wake-up source is not released in error conditions. Fix the same.
CRs-Fixed: 977956
Change-Id: I816642281aa2663b504ef3532653ff49aecc4f30
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
This reverts 'commit 9890d1939491 ("driver: lpm-workarounds:
disable/enable L2 low power modes")' as power regression seen
with disabling L2 low power modes.
Change-Id: I2a4fea67a62065c64bfa7ec3af8a20a18480dd13
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
when device battery capacity is less than 2%, PLL turn on
through spm is not working and causing lpm workarounds to
get struck in infinite loop.
Register for power supply notifications and postpone the
L1/L2 dynamic clock gating enablement till battery reach
safe level.
Change-Id: I21acdc6b097937bc54a06b72434e0a0a61570b8a
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
Fix the register offset for IMA_CFG register. Also, perform the
exception clear sequence if IACS_READY check fails.
While at it, change the error level for beat count mismatch
during IMA access.
CRs-Fixed: 894358
Change-Id: Id1d4b797ff1bbea41c91790b956bd87cca042957
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
Incorrect wakeup source was acquired before scheduling iadc gain
compensation. Fix the same.
Change-Id: I439c1c20d71a72ef9ab02fc916fa8c0dae03ea0a
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
Currently, MAH_TO_SOC_CONV_REG is read and the data is converted
to half float before dividing it by the learned capacity.
However, it should not be converted like that and should be used
as an unsigned integer instead. Also, before dividing it by the
learned capacity, convert it to MICRO_UNIT so that the floating
point encoding of cc_to_soc coefficient will be proper. Fix it.
CRs-Fixed: 887349
Change-Id: Ibbeca6f2aff24fc68bc8bf931fa03850ca22c3a9
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Add support to detect the damaged battery when the safety-timer expires
by using the coulomb count. This feature is applicable only for PMi8952
V2.0 FG and the future PMi chips.
CRs-Fixed: 866074
Change-Id: I36bbfac5cea741ab64c7ff2bdeb786d907c101f8
Signed-off-by: Chunmei Cai <ccai@codeaurora.org>
When IADC gain compensation is enabled, gain value should
be stored in SRAM register 0x425 as specified in the
documentation. Fix SRAM register address to 0x425 in gain
reset condition.
CRs-Fixed: 886608
Change-Id: I56aa48d3b7e2960fc9f1afd8534d93c34b982114
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
PMI8950 v2.0 supports coulomb counting in hardware which can
be used for capacity learning. Enable this feature.
CRs-Fixed: 860869
Change-Id: I2450ade3d30683effe92ad1be5c4db735a507b06
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
In the case of internal current sensing IADC gain has dependency
on VBAT during discharge. Add support for gain compensation to
negate the effect of VBAT.
CRs-Fixed: 859531
Change-Id: Ic80b1fb853cad88aae4351abeaf573d37bc1ec54
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
Add support for the optional property qcom,hold-soc-while-full. When
this property is defined, the fuel gauge driver will report 100% SoC
whenever the battery is full.
CRs-Fixed: 864029
Change-Id: Ide23402f04e1ed71c4d8d9839522e4198b222e35
Signed-off-by: Xiaozhe Shi <xiaozhes@codeaurora.org>
Add support for JEITA hysteresis and allow it to be configured
through "qcom,cold-hot-jeita-hysteresis" device tree property.
CRs-Fixed: 866616
Signed-off-by: Qiang Huang <qianghuang@codeaurora.org>
Change-Id: I902080978701a1853531496e4afdd85ecf972b0d
Currently, we configure the FG SRAM register 0x4AF only if the
qcom,sw-rbias-control property is specified through device tree.
However, if that property is not specified for a device anymore
where it was specified before, previous configuration would be
retained unless there is a dVdd reset. Reconfigure the register
0x4AF to allow the default thermistor settings in such cases.
CRs-Fixed: 880044
Change-Id: Ic9bbea3d68968c39bf9b66532278178de9104b24
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
When capacity learning feedback is enabled, cc_to_soc
coefficient should get stored in SRAM register 0x578
as specified in the documentation. Fix it.
CRs-Fixed: 870383
Change-Id: Icd8e2770d7060e99388c845e991a2555bff4ba4d
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Bucket based cycle counter implementation allows user-space
to set the bucket-id and read counter associated with the bucket.
There is a possibility of setting bucket-id beyond maximum bucket
count resulting in out of bound array access.
Fix this by adding check to reject bucket-id if it is greater than
maximum bucket size.
CRs-Fixed: 847140
Change-Id: I9c0e9a7687fa3e765fe15a98176177d12a92b33d
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
Currently the fuel gauge driver only allows resume SOCs of 0-100.
However, the fuel gauge hardware allows for higher accuracy resume SOCs
of 0-255. Support this in the driver by adding the resume-soc-raw
property.
Also, fine tune the reported SOC. 0% SOC should only be reported when
the SOC is 0, and 100% SOC should only be reported when the SOC is full.
Change the report function to reflect this.
CRs-Fixed: 857620, 844543
Change-Id: Ib7513bf5c53c94cbb655eb0934472e912bc3f805
Signed-off-by: Xiaozhe Shi <xiaozhes@codeaurora.org>
Currently, cycle counter gets incremented only when the charging
happens within the specified low and high soc thresholds. Instead
of that, implement the bucket based cycle counter algorithm which
increments the counters based on multiple charging buckets. This
helps to study the charging pattern.
For example, with a bucket count of 8, if the user charges from 5
to 30% and removes the charger, cycle counter for buckets 1 and 2
would get incremented. This bucket based cycle counters will be
available to the userspace via cycle_count property after the
cycle_count_id property is set to specify which bucket needs to
be read.
For example, to read cycle count for bucket 4, following helps.
echo 4 > /sys/class/power_supply/bms/cycle_count_id
cat /sys/class/power_supply/bms/cycle_count
Since this algorithm operates on all the SOC levels (0-100%),
there is no need for low and high SOC thresolds. Remove them.
CRs-Fixed: 847140
Change-Id: I1c0840f01693909586cafb3d51685637f3a6d2ba
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Currently, FG SRAM parameters are updated once every 30 seconds.
However, there are cases where the user wants to see the SRAM
parameters getting updated as soon as the charging status
changes e.g. from charging to discharging. Update the SRAM
parameters if the status changes and the last update of SRAM
parameters was done 5 seconds before.
While at it, remove the prev_status defined under learning data
as it is not used at all.
CRs-Fixed: 860061
Change-Id: Id5b97a29cf7d67a317d71726a126060852fba913
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
The bias current is identified only by the lower two bits, and its
value can be 1, 2, or 3. The current bounds check is incorrect. Fix
it.
CRs-Fixed: 857879
Change-Id: Icf34d1144904b9d41f5181625dcf598c247e33d3
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
Capacity learning feedback is needed for the capacity learning
algorithm. It will be supported based on the following device
tree property "qcom,capacity-learning-feedback" and will work
only when the capacity learning is enabled.
CRs-Fixed: 848838
Change-Id: Idde0d3aa6e8a3aafeadf5f90e2118ceed2c96b5f
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Add support to read thermal coefficients from battery profile.
If thermal coefficient is present in FG DT node then it will always
takes precedence over the configuration present in battery profile.
CRs-Fixed: 853464
Change-Id: Iea876b9d4f7777028d0aed5a79ff3d5dada1f8b6
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
Add an additional check to the capacity learning algorithm's start
conditions to make sure that the battery is reasonably well settled
before starting. Specifically, check that the difference between
vbat_shadow and the v_current_predicted is not greater than a specified
threshold before starting the algorithm.
CRs-Fixed: 827068
Change-Id: Ief96061c69d26c8ebbf4cf374c3e0f7ef5933017
Signed-off-by: Xiaozhe Shi <xiaozhes@codeaurora.org>
Currently the fuel gauge driver only reads CPRED_VOLTAGE until the
battery profile is loaded. This is incorrect, as this value is also used
by the driver to report to userspace. Change the conditional check on
the SRAM parameter enums so that the update_sram function always read
CPRED_VOLTAGE whenever the sram is being refreshed.
CRs-Fixed: 827068
Change-Id: I2f951c40d40bf95b95cda883b3378e764f6b5baf
Signed-off-by: Xiaozhe Shi <xiaozhes@codeaurora.org>
Add support to read CC-CV threshold configuration from battery profile.
If CC-CV threshold is present in FG DT node then it will always takes
precedence over the configuration present in battery profile.
CRs-Fixed: 847161
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
Change-Id: I40562f50247b4674726a7ac6364b8b91d7440309
In case of Interleave Memory Access(IMA) protocol, software
needs to wait and poll for IACS Ready bit to be set across
each read/write operation.
FG hardware updates IACS bit 20-30 usec after the read/write
operation. Add a delay of 30 usec before reading IACS bit to
make sure FG hardware gets time to update (this reduces number
of polling retries and overall read/write time).
Change-Id: I4866c82f30d9271fa8bead09d26ec7eaba6f1f2b
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
Commit c430141935 ("power:
qpnp-fg: reduce the probe time of driver) moved the hardware
initialization to delayed_init_work to improve the driver probe
time. However, with the recent change made in update_sram_data
to wait for SRAM access to be revoked before updating SRAM
parameters times out because the access is held by the callee
itself.
This eventually causes error in fg_batt_profile_init as below.
[ 9.547366] FG: fg_hw_init: set default value to esr filter
[ 12.542896] FG: update_sram_data_work: transaction timed out ret=0
[ 17.539999] FG: fg_batt_profile_init: profile loading timed out rc=-110
[ 17.545583] FG: batt_profile_init: failed to initialize profile
Fix this.
CRs-Fixed: 844197
Change-Id: I16f52f991ccccc275a945874bfe86259a5ec97f1
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Currently battery missing interrupt is handled in an interrupt
handler. There are some situations where it can sleep. Hence
move it to a threaded interrupt handler to handle that.
While at it, fix the error return code handling when the
interrupt registration fails.
CRs-Fixed: 837984
Change-Id: I5a79f24d809809cbef7b8b93e9942b72b1bfc335
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Currently when the fuel gauge driver probes, hardware init and
updating SRAM parameters consumes more time because of the
internal SRAM access adding up to the delay.
Move these functions from the probe to a scheduled work so that
the driver probe function can finish up early improving up the
boot time.
Also, move the fg_hw_init routine to the front of the
initialization work in order to ensure that the hardware gets
initialized before the SRAM parameters are read.
CRs-Fixed: 835416
Change-Id: I410be1c2e9093b0f238b2affcee0f7c694a3eaee
Signed-off-by: Jie Cheng <rockiec@codeaurora.org>
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Add support to modify the fuel gauge sram refresh rate via the module
parameter sram_update_period_ms.
Change-Id: I94dab77d15c66f944a35ec644a95d746a68f3d43
Signed-off-by: Xiaozhe Shi <xiaozhes@codeaurora.org>
Add the module parameter "restart" to the fuel gauge driver. Writing
into this parameter will issue a restart command to the fuel gauge,
restarting the fuel gauge internal SOC variables.
While the restart is progressing, the module parameter will read 1.
Otherwise it will read 0.
CRs-Fixed: 819622
Change-Id: I92a84491900affae85427eae2351da810a6eea27
Signed-off-by: Xiaozhe Shi <xiaozhes@codeaurora.org>
In the fuel gauge, the rslow is the capacitive resistance in the
battery. Since this changes over time, it cannot be easily sensed by the
fuel gauge's ESR detection. Instead, the value is provided by a constant
in the battery profile.
However, the rslow was found to change when charging at different
battery state of charges. The changes in rslow can cause up to 2-3% of
SoC error when charging in an almost full state.
Fix this by using differently profiled rslow data when charging at over
a set threshold.
CRs-Fixed: 768722
Change-Id: I7c61782c6ab9c4a97bb3a87aea8dc7e9eab6534b
Signed-off-by: Xiaozhe Shi <xiaozhes@codeaurora.org>
64-bit division fails compilation on AArch32 if arithmetic
division operator is directly used for division.
Use div64_s64/do_div APIs for 64-bit division operations.
Change-Id: I0324b061fbe7ff5105e271ae0e13bc51010f04d3
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
The fuel gauge driver is overwriting the battery profile's charge
termination and cc_to_cv set point during probe. The fuel gauge
driver checks whether the profile loaded in SRAM is the same as
the one that it loads from device tree in order to decide whether
a fuel gauge restart is needed.
With the current driver overwriting the charge termination and
CC to CV setpoint, the profile will always differ from the one
loaded from device tree. Thus, the driver will restart the
fuel gauge every single time it probes.
This can cause large fuel gauge accuracy drops at power-on because
instead of using the old converged SOC, it has to estimate a new one
based on voltage.
Fix this issue by only comparing the first 32 bytes of the battery
profile, which should be dynamically set, to determine whether a new
profile needs to be loaded.
CRs-Fixed: 821074
Change-Id: I809a70f4ef8411ebbab71539316f1e5a0c128f27
Signed-off-by: Xiaozhe Shi <xiaozhes@codeaurora.org>
Currently vbatt_low interrupt is kept enabled all the time.
However, there are scenarios where the battery voltage can
fluctuate and cause vbatt_low interrupt firing frequently.
To help with such scenarios, disable the vbatt_low interrupt
once the interrupt fires on crossing over vbatt_low threshold
or when the charger is disconnected. Enable it only when the
charger is connected again.
CRs-Fixed: 817649
Change-Id: I6cde453f3fbc4638a27e4a46d694fd1d97275366
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Report the fuel gauge battery soc, coulomb counter soc, and
voltage/intergrator error through the power supply framework.
CRs-Fixed: 808597
Change-Id: Ibd107bdd0cafe7bfdcbc562be984a8a84b604fd0
Signed-off-by: Xiaozhe Shi <xiaozhes@codeaurora.org>
As per the PMIC systems team recommendation, improve the ESR
detection during cold battery condition to prevent jumps in
detected value. Update the ESR filter values to achieve that.
CRs-Fixed: 812179
Change-Id: Ief214925861a5df69e9cf9f8b4f69f491f59d671
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Currently, while updating fuel gauge SRAM data, an incorrect
conditional check is made before releasing the access of memory
interface. Fix that.
CRs-Fixed: 814119
Change-Id: I7ad8017470ede797bf2970d405f8ac5650417484
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Wei Wang
LuK1337
Subbaraman Narayanamurthy
Ashay Jaiswal
Maulik Shah
Anji Jonnala
Yadav Anamika
Linux Build Service Account
Chunmei Cai
Xiaozhe Shi
Qiang Huang
Nicholas Troast
Jie Cheng