Add logic to choose between multiple ACC override configurations
based on the override fuse. The scheme maps each possible override
fuse value to a override configuration.
Update 8952 and 8939 ACC DT configuration accordingly.
CRs-Fixed: 896763
Change-Id: Ia5cc395edab3d9fe34c94af5457462a677b59399
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Some targets need to change mem-acc-type registers for mode switching. Add
optional device tree properties and driver support for the need.
CRs-Fixed: 780594
CRs-Fixed: 780605
Change-Id: I14913d7fbfb73bd88f675752b30bf6f469380656
Signed-off-by: Ke Liu <keliu@codeaurora.org>
Some targets need override ACC configuration for ACC_SEL, L1/L2 custom
data to be applied based on allocated fuse bit. Add support to read
allocated fuse selection bit and apply the override configuration if
the fuse bit is set.
CRs-Fixed: 775309
Change-Id: I34690c245dbbe7914b36f6810eadd735002cc4bb
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
Some targets need specific data to be configured into L1 and L2
CUSTOM_ACC registers across APC corner switch. Add support to
pass custom register addresses and configuration data through
device tree.
CRs-Fixed: 715818
Change-Id: I96245382d3980f96ec7a1eea5d680284939ae925
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
The scm library has added support for a new secure world
interface that is more aligned to the ARMv8 SMC calling
convention. Use the new API while maintaining backward
compatibility.
Change-Id: Ia6e5ab948f31c03cfcf7d1391154c18148b7099f
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Some targets share a single ACC control register between two
independent application processor clusters. Add locking around
ACC register updating calls in order to guarantee mutual
exclusion between the clusters on these targets.
Change-Id: If3bfdd6b6e798fafed4df9131b5620172cacd72f
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add support for arbitrary L1 and L2 memory accelerator selector
sizes. The default value of 2 is not sufficient for all targets.
Provide this support via a pair of new device tree properties.
Change-Id: I8c625e16852451be500c711c4011971fd7dfce34
Signed-off-by: David Collins <collinsd@codeaurora.org>
On some targets both the L1 and L2 ACC configuration
bits are located in the same register. Caching this
register per memory may lead to incorrect ACC values
being programmed. Fix this by always using the latest
ACC configuration from the memory.
Change-Id: Ie3ab96666f6db98559332afd0349d464a5ad1348
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Add a fuse based logic to skip the L1 memory ACC configuration. This is
required on some parts.
CRs-Fixed: 680261
Change-Id: Id07d65b8482f63e114ec6ae3b3fc3b961235d846
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
Compiling the kernel with the -O2 GCC flag reveals a number
of warnings relating to potentially uninitialized variables
and other edge cases.
Change-Id: I3758dbe1af276d79f55188b9f2db850c730acb80
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
The memory accelerator (MEM ACC) controls the delays applied during
memory access. These delays vary based on the power-mode (corner)
on which the memory is connected. This driver adds a regulator
interface to configure the power-mode of the memory accelerator
based on the APC (application processor) corner.
Change-Id: I830ff000f8a16c4d3de5bdebf48d424354ddb086
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Anirudh Ghayal
Ke Liu
Tirupathi Reddy
Linux Build Service Account
Vikram Mulukutla
David Collins
Stepan Moskovchenko