Add user space interface to the SPMI kernel framework that enables
master-read and master-write transactions.
Each SPMI controller is represented as a file under the root directory
of SPMI debug-fs. For each controller, 'address', 'count', and 'data'
files are added. The user may configure the transaction via the
respective files and invoke a master read transaction by reading from
the 'data' file, and a master write transaction by writing a string of
decimal or hexadecimal byte size values to the 'data' file.
Change-Id: I3e760be7796bfb9aa15c8ab758ff616a72240176
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
Signed-off-by: Kenneth Heitke <kheitke@codeaurora.org>
It turns out that the only use cases for the qpnp library use
the existing spmi data structures. As such, there's really
no justification for having the library not be called 'spmi'.
There is nothing Qualcomm specific about this code.
Also cleanup some inconsistencies in the Kernel Doc comments
while we're here.
Change-Id: I1c73c88be740b6f5d38ba2de62de1737981b30fa
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
QPNP is a Qualcomm SPMI based implementation that specifies 256
devices per SPMI slave ID, with up to 8 interrupts per device.
This brings the theoretical max interrupt support to 32768 per
bus for this architecture.
This driver implements the standard irq chip interfaces to
support QPNP. The chip driver is informed of Device Tree
configuration through a notifier interface. Once informed of an
interrupt, it will allocate resources on the fly. In order to
support this large logical interrupt range, we require SPARSE_IRQ
to be enabled.
This driver supports Device Tree interrupt specs with a cell size
of three. These are comprised of the the slave ID, peripheral ID
and irq number.
Change-Id: Ic7847bafe6598a84ab3650df7c95bb605aefbe62
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
QPNP is a SPMI based PMIC architecture developed by Qualcomm.
This library constitutes routines that should be necessary for
most, if not all QPNP based devices. The goal is to minimize the
amount of code duplication.
Change-Id: I0fddfcef88416bba488480d790d1cf361d9e67ac
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Qualcomm's PMIC Arbiter SPMI controller functions as a bus master and
is used to communication with one or more PMIC (slave) devices on the
SPMI bus. The PMIC Arbiter is actually a hardware wrapper around the
SPMI controller that provides concurrent and autonomous PMIC access
to various entities that need to communicate with the PMIC.
The SPMI controller hardware handles all of the SPMI bus activity (bus
arbitration, sequence start condition, transmission of frames, etc).
This software driver uses the PMIC Arbiter register interface to
initiate command sequences on the SPMI bus. The status register is
read to determine when the command sequence has completed and whether
or not it completed successfully.
Request Capable Slave (RCS) devices can initiate a master write
command sequence on the SPMI bus that the can be decoded by the
bus master and used to generate interrupts.
Change-Id: I037fefc946ccb5b8e0b04da856a3a96effe1c7e4
Signed-off-by: Kenneth Heitke <kheitke@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
SPMI (System Power Management Interface) is a specification
developed by the MIPI (Mobile Industry Process Interface) Alliance
optimized for the real time control of Power Management ICs (PMIC).
SPMI is a two-wire serial interface that supports up to 4 master
devices and up to 16 logical slaves. A physical PMIC device may
consist of multiple logical slave interfaces.
The framework supports message APIs, multiple busses (1 controller
per bus) and multiple clients/slave devices per controller.
Change-Id: Ib6319047b4ab9cea6dfb0879312c4c1f63462439
Signed-off-by: Kenneth Heitke <kheitke@codeaurora.org>
Kenneth Heitke
Michael Bohan