Commit graph

93 commits

Author SHA1 Message Date
David S. Miller
ed39f731ab [TG3]: Update driver version and release date.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-10-03 16:25:23 -07:00
Michael Chan
399de50bbb [TG3]: Refine AMD K8 write-reorder chipset test.
Test for VIA K8T800 north bridge instead of AMD K8 HyperTransport
bridge based on new information from Andi Kleen. The AMD
HyperTransport interface is not responsible for PCI transactions
and so the re-ordering is more likely done by the VIA north bridge.
This code is subject to change if we get more information from AMD
or VIA.

PCI Express devices are excluded from doing the read flush since all
chipsets in the write_reorder list are PCI chipsets.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-10-03 14:02:39 -07:00
David S. Miller
c8a6c29639 [TG3]: Update driver version and release date.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-27 12:13:38 -07:00
Michael Chan
f9804ddbee [TG3]: misc. fixes
Fix interrupt test handler by adding check for IRQ assertion in
PCI_STATE register in addition to the status block updated bit.

Add test for valid ethernet address in tg3_set_mac_addr().

Add tg3_bus_string() to setup the PCI bus speed/width string for all
PCI/PCIX/PCI Express devices. This is used to print the bus type
during init_one().

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-27 12:13:10 -07:00
Michael Chan
c94e39418a [TG3]: 5780 PHY fixes
Fix 5780 PHY related problems:

1. MAC_RX_MODE reset must be done before setting up the MAC_MODE
   register on 5705_PLUS chips or the chip will stop receiving after
   a while. The MAC_RX_MODE reset is needed to prevent intermittently
   losing the first receive packet on serdes chips.

2. Skip MAC loopback test on 5780 because of hardware errata. Normal
   traffic including PHY loopback is not affected by the errata.

3. PHY loopback fails intermittently on 5708S and this is fixed by
   putting the PHY in loopback mode first before programming the MAC
   mode register. A MAC_RX_MODE reset is also added.

4. Return -EINVAL in tg3_nway_reset() if device is in TBI mode. Allow
   nway_reset if 5780S is in parallel detect mode.

5. Add missing PHY IDs in KNOWN_PHY_ID() macro.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-27 12:12:42 -07:00
Michael Chan
c58ec93245 [TG3]: Fix 4GB boundary tx handling
Fix and simplify the workaround code for the 4GB boundary tx buffer
hardware bug.

1. Need to unmap the original SKB's dma addresses if a new SKB cannot
   be allocated.

2. Need to pass the base flag to tigon3_4gb_hwbug_workaround() or TSO
   won't work properly.

3. The guilty entry and length parameters for
   tigon3_4gb_hwbug_workaround() are removed as they are not necessary.

4. Remove assumption that only one fragment can hit the 4GB boundary.
   Another fragment can hit 8GB for example.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-17 00:46:27 -07:00
Peter Hagervall
22abe310bc [TG3]: Sparse fixes for tg3
Change 0 to NULL where appropriate.

Signed-off-by: Peter Hagervall <hager@cs.umu.se>
Acked-by: Jeff Garzik <jgarzik@pobox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-16 17:01:03 -07:00
David S. Miller
1cbf07478b [TG3]: Add AMD K8 to list of write-reorder chipsets.
Thanks to Andy Stewart for the report and testing
debug patches from Michael Chan.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-16 16:59:20 -07:00
John W. Linville
2ff436977e [TG3]: Add support for ETHTOOL_GPERMADDR.
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-12 14:44:20 -07:00
John W. Linville
4f63b87772 [TG3]: Do not count non-error frames dropped by the hardware as rx_errors.
Instead, count them as part of rx_missed_errors.

Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-12 14:43:18 -07:00
David S. Miller
74da1edf26 [TG3]: Update driver version and release date.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-05 17:56:11 -07:00
Michael Chan
38f3843ed6 [TG3]: Use status tag to check for new events
Use the status tag to determine if there are new events in
tg3_interrupt_tagged(). We discussed about this a while ago with Grant
Grundler and DaveM. This scheme makes it unnecessary to clear the
updated bit in the status block when using tagged mode, and only
a simple comparison is needed to determine if there are new events.

The tp->lock around netif_rx_complete() and tg3_restart_ints() is also
removed. It is unnecessary with DaveM's new locking scheme.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-05 17:53:32 -07:00
Michael Chan
61487480dd [TG3]: Remove status block access in tg3_msi() and add prefetches
Remove unnecessary status block accesses in tg3_msi(). Since MSI is
not shared, it is unnecessary to read the status block to determine if
there are any new events in the MSI handler. It is also unnecessary to
clear the updated bit in the status block.

Since the poll list is per-cpu, tg3_poll() will be scheduled to run on
the same CPU that received the MSI. Prefetches for the status block
and the next rx descriptors are added in tg3_msi() to improve their
access times when tg3_poll() runs.

In the non-MSI irq handlers, we need to check the status block because
interrupts may be shared. Only prefetches for the next rx descriptors
are added.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-05 17:53:19 -07:00
Michael Chan
9f40dead25 [TG3]: Add PHY loopback test
Improve ethtool loopback self test by adding PHY loopback to the
existing MAC loopback test.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-05 17:53:06 -07:00
Michael Chan
4009a93d8e [TG3]: Add ethtool -p support
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-05 17:52:54 -07:00
Michael Chan
4c98748763 [TG3]: Minor 5780 and 5752 fixes
Minor SerDes bug fixes for 5780S and nvram bug fixes for 5780 and
5752.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-05 17:52:38 -07:00
David S. Miller
75c80c382f [TG3]: Update driver version and release date.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-01 17:42:23 -07:00
Michael Chan
51b9146869 [TG3]: Minimize locking in TX path.
This is similar to Eric Dumazet's tx_lock patch for tg3 but takes it
one step further to eliminate the tx_lock in the tx_completion path
when the tx queue is not stopped.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-01 17:41:28 -07:00
Michael Chan
087fe256f0 [TG3]: Fix bug in setting a tg3_flag
Found a bug while reviewing the patches the second time.

The TG3_FLAG_TXD_MBOX_HWBUG flag is set after the register access
methods have been determined. This patch fixes it by moving it up before
the various access methods are assigned.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-08-29 15:50:49 -07:00
Michael Chan
15f5a585c6 [TG3]: Eliminate one register write in tg3_restart_ints()
The register write to register 0x68 to restart interrupts is unnecessary
as the interrupt wasn't masked in that register by the irq handler. This
will save one register write in the fast path.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-08-29 15:50:45 -07:00
Michael Chan
6892914fb7 [TG3]: Add indirect register method for 5703 behind ICH
This patch adds the new workaround for 5703 A1/A2 if it is behind
certain ICH bridges. The workaround disables memory and uses config.
cycles only to access all registers. The 5702/03 chips can mistakenly
decode the special cycles from the ICH chipsets as memory write cycles,
causing corruption of register and memory space. Only certain ICH
bridges will drive special cycles with non-zero data during the address
phase which can fall within the 5703's address range. This is not an ICH
bug as the PCI spec allows non-zero address during special cycles.
However, only these ICH bridges are known to drive non-zero addresses
during special cycles.

The indirect_lock is also changed to spin_lock_irqsave from spin_lock_bh
because it is used in irq handler when using the indirect method to
disable interrupts.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-08-29 15:50:42 -07:00
Michael Chan
09ee929ccc [TG3]: Add mailbox read method
This patch adds the mailbox read method and also adds an inline function
tw32_mailbox_f() for mailbox writes that require read flush.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-08-29 15:50:38 -07:00
Michael Chan
1ee582d8e4 [TG3]: Add various register methods
This patch adds various dedicated register read/write methods for the
existing workarounds, including PCIX target workaround, write with read
flush, etc. The chips that require these workarounds will use these
dedicated access functions.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-08-29 15:50:15 -07:00
Michael Chan
2009493065 [TG3]: Add basic register access function pointers
This patch adds the basic function pointers to do register accesses in
the fast path. This was suggested by David Miller. The idea is that
various register access methods for different hardware errata can easily
be implemented with these function pointers and performance will not be
degraded on chips that use normal register access methods.

The various register read write macros (e.g. tw32, tr32, tw32_mailbox)
are redefined to call the function pointers.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-08-29 15:50:12 -07:00
Michael Chan
d4ef160889 [TG3]: Fix ethtool loopback test lockup
The tg3_abort_hw() call in tg3_test_loopback() is causing lockups on
some devices. tg3_abort_hw() disables the memory arbiter, causing
tg3_reset_hw() to hang when it tries to write the pre-reset signature.
tg3_abort_hw() should only be called after the pre-reset signature has
been written. This is all done in tg3_reset_hw() so the tg3_abort_hw()
call is unnecessary and can be removed.

[ Also bump driver version and release date. -DaveM ]

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-08-25 15:31:41 -07:00
David S. Miller
034ea6388a [TG3]: Update driver version and reldate.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-08-19 12:57:31 -07:00
Michael Chan
da6b2d01d6 [TG3]: Fix SerDes detection
A problem was reported by Grant Grundler on an HP rx8620 using IOX
Core LAN partno(A7109-6) 5701 copper NIC. The tg3 driver mistakenly
detects this NIC as having a SerDes PHY and link does not come up as a
result.

The problem was caused by an incorrectly programmed eeprom that set the
NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER bit in the NIC_SRAM_DATA_CFG location.

This patch will override the NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER bit if a
valid PHY ID is read from the MII registers on older 570x chips where
the MII interface is not used on SerDes chips. On newer chips such as
the 5780 that use MII for both copper and SerDes, SerDes detection must
rely on the eeprom.

This patch will make the SerDes detection identical to versions 3.25 and
older.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Acked-by: Grant Grundler <iod00d@hp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-08-19 12:54:29 -07:00
David S. Miller
7d3f4c9772 [TG3]: Save initial PCI state before registering the netdevice.
Else on SMP systems it is possible for hotplug to execute,
invoke tg3_open(), and end up loading the uninitialized
PCI register save area into the card.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-08-06 06:35:48 -07:00
David S. Miller
fc87670b6c [TG3]: Update driver version and reldate.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-07-25 12:45:32 -07:00
Michael Chan
747e8f8bff [TG3]: add 5780 fiber support
Add 5780S support by adding a new tg3_setup_fiber_mii_phy() function and
a timer function for parallel link detection. 5780S uses standard MII
registers for 1000BaseX and runs in GMII mode as opposed to TBI mode on
older serdes chips.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-07-25 12:33:22 -07:00
Michael Chan
ef7f5ec0de [TG3]: disallow jumbo TSO on 5780
Disallow jumbo TSO on 5780 due to hardware restrictions.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-07-25 12:32:25 -07:00
Michael Chan
fdfec1726b [TG3]: consolidate all DMA water mark settings
Consolidate all DMA watermark settings for standard and jumbo frames on
all chips in tg3_init_bufmgr_config() and add new settings for 5780.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-07-25 12:31:48 -07:00
Michael Chan
7e72aad48c [TG3]: add variable buffer size for standard ring
Add a new rx_pkt_buf_sz to the tg3 structure to support variable buffer
sizes on the standard ring.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-07-25 12:31:17 -07:00
Michael Chan
0f893dc6ec [TG3]: add 5780 basic jumbo frame support
Add basic jumbo frames support for 5780. This chip supports jumbo frames
on the standard receive ring without the jumbo ring. The
TG3_FLAG_JUMBO_ENABLE is changed to TG3_FLAG_JUMBO_RING_ENABLE to
indicate using the jumbo ring on 5704 and older chips. A new
TG3_FLG2_JUMBO_CAPABLE flag is added to indicate jumbo frames support
with or without the jumbo ring.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-07-25 12:30:38 -07:00
Michael Chan
4cf78e4fb6 [TG3]: add 5780 basic support
Add 5780 PCI IDs, chip IDs, and other basic support.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-07-25 12:29:19 -07:00
David S. Miller
93e266f600 [TG3]: Update driver version and reldate.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-07-05 14:43:19 -07:00
Michael Chan
d244c892c8 [TG3]: support for ethtool -C
Add support for ethtool -C with verification of user parameters.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-07-05 14:42:33 -07:00
David S. Miller
5f70eaa0d5 [TG3]: Update driver version and reldate.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-24 20:21:01 -07:00
Michael Chan
bbe832c092 [TG3]: Refinements to new locking strategy.
1. Move tp->irq_sync = 0 to before the interrupt mailbox IO in
   tg3_enable_ints() so that the interrupt handler will always see
   irq_sync == 0 when interrupts are enabled.

2. Remove the tg3_enable_ints() call in tg3_reset_hw(). Interrupts are
   always enabled explicitly or through tg3_netif_start(). This is to
   prevent interrupts being enabled while poll is disabled.

3. Update trans_start with jiffies in tg3_netif_stop() to prevent false
   NETDEV WATCHDOG.

4. Pass in the proper irq_sync parameter to tg3_full_lock() depending on
   netif_running() in some of the ethtool set calls.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-24 20:20:04 -07:00
David S. Miller
f47c11eecc [TG3]: Eliminate all hw IRQ handler spinlocks.
Move all driver spinlocks to be taken at sw IRQ
context only.

This fixes the skb_copy() we were doing with hw
IRQs disabled (which is illegal and triggers a
BUG() with HIGHMEM enabled).  It also simplifies
the locking all over the driver tremendously.

We accomplish this feat by creating a special
sequence to synchronize with the hw IRQ handler
using a binary state and synchronize_irq().
This idea is from Herbert Xu.

Thanks to Michael Chan for helping to track down
all of the race conditions in initial versions
of this code.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-24 20:18:35 -07:00
David S. Miller
cd024c8baf [TG3]: Fix missing memory barriers and SD_STATUS_UPDATED bit clearing.
There must be a rmb() between reading the status block tag
and calling tg3_has_work().  This was missing in tg3_mis()
and tg3_interrupt_tagged().  tg3_poll() got it right.

Also, SD_STATUS_UPDATED must be cleared in the status block
right before we call tg3_has_work().  Only tg3_poll() got this
wrong.

Based upon patches and commentary from Grant Grundler and
Michael Chan.

Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-24 20:17:10 -07:00
David S. Miller
ed7fce6c13 [TG3]: Update driver version and release date.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-08 14:15:52 -07:00
Michael Chan
6d1cfbab4d [TG3]: Fix 5700/5701 DMA corruption on Apple G4.
Fix 5700/5701 DMA write corruption on Apple G4 by detecting the Apple
UniNorth PCI 1.5 chipset and adjusting the DMA write boundary to 16. DMA
test fails to detect the problem with this chipset.

Thanks to Manuel Perez Ayala for reporting the problem and helping to
debug it.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-08 14:13:14 -07:00
David S. Miller
15def7bfb6 [TG3]: Update driver version and release date.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-06 15:22:56 -07:00
Michael Chan
9ba2779419 [TG3] Fix link failure in 5701
On some 5701 devices with older bootcode, the LED configuration bits in
SRAM may be invalid with value zero. The fix is to check for invalid
bits (0) and default to PHY 1 mode. Incorrect LED mode will lead to
error in programming the PHY.

Thanks to Grant Grundler for debugging the problem.

>From Grant:
| In May, 2004,  tg3 v3.4 changed how MAC_LED_CTRL (0x40c) was getting
| programmed and how to determine what to program into LED_CTRL. The new
| code trusted NIC_SRAM_DATA_CFG (0x00000b58) to indicate what to write
| to LED_CTRL and MII EXT_CTRL registers. On "IOX Core Lan", SRAM was
| saying MODE_MAC (0x0) and that doesn't work.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-06 15:16:20 -07:00
Michael Chan
49cabf49ab [TG3]: Add TSO firmware license
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-06 15:15:17 -07:00
Michael Chan
1b62815193 [TG3]: Fix bug in tg3_load_firmware_cpu
Add tg3_nvram_lock() and tg3_nvram_unlock() calls around tg3_halt_cpu().
It is possible that the bootcode may be loading code from nvram during
this call and stopping the cpu without getting the lock may cause
uncompleted nvram data to be left in the nvram data register. Subsequent
calls to read/write nvram data will fail.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-05-29 14:59:49 -07:00
Michael Chan
d4bc3927d2 [TG3]: Add interrupt test
This test uses the previously added tg3_test_interrupt() to perform the
test.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-05-29 14:59:20 -07:00
Michael Chan
c76949a682 [TG3]: Add loopback test
The test will loopback one packet in MAC loopback mode and verify the
packet data.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-05-29 14:58:59 -07:00
Michael Chan
7942e1dbd7 [TG3]: Add memory test
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-05-29 14:58:36 -07:00