Commit graph

6 commits

Author SHA1 Message Date
Sergei Shtylyov
dd99d9661c [MIPS] Alchemy: fix PCI resource conflict
... by getting the PCI resources back into the 32-bit range -- there's no
need therefore for CONFIG_RESOURCES_64BIT either. This makes Alchemy PCI
work again while currently the kernel skips the bus scan.

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-12-14 17:34:29 +00:00
Ralf Baechle
940f6b48a1 [MIPS] Only build r4k clocksource for systems that work ok with it.
In particular as-is it's not suited for multicore and mutiprocessors
systems where there is on guarantee that the counter are synchronized
or running from the same clock at all.  This broke Sibyte and probably
others since the "[MIPS] Handle R4000/R4400 mfc0 from count register."
commit.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-26 17:26:14 +00:00
Ralf Baechle
42f77542f4 [MIPS] time: Move R4000 clockevent device code to separate configurable file
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-18 18:11:47 +01:00
Ralf Baechle
f3e8d1da38 [MIPS] Alchemy: Fix build by conversion to irq_cpu.c.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-17 18:28:48 +01:00
Ralf Baechle
d806cb2b60 [MIPS] Kconfig: Enable 64BIT_PHYS_ADDR only through select.
The user should not have to have any clue about this setting.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-08-27 02:16:49 +01:00
Yoichi Yuasa
c3543e253a [MIPS] Separate Alchemy processor based boards config
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-05-11 14:28:33 +01:00