Commit graph

22 commits

Author SHA1 Message Date
Russell King
ad1ae2fe7f [ARM] Unuse another Linux PTE bit
L_PTE_ASID is not really required to be stored in every PTE, since we
can identify it via the address passed to set_pte_at().  So, create
set_pte_ext() which takes the address of the PTE to set, the Linux
PTE value, and the additional CPU PTE bits which aren't encoded in
the Linux PTE value.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-13 14:34:43 +00:00
Russell King
94b1e96d9d [ARM] Formalise the ARMv6 processor name string
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-08 16:05:52 +00:00
Russell King
efe90d273b [ARM] Handle HWCAP_VFP in VFP support code
Don't set HWCAP_VFP in the processor support file; not only does it
depend on the processor features, but it also depends on the support
code being present.  Therefore, only set it if the support code
detects that we have a VFP coprocessor attached.

Also, move the VFP handling of the coprocessor access register into
the VFP support code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-08 16:05:26 +00:00
Russell King
ee90dabcad [ARM] Include asm/elf.h instead of asm/procinfo.h
These files want to provide/access ELF hwcap information, so should
be including asm/elf.h rather than asm/procinfo.h

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-11-30 12:24:46 +00:00
Russell King
3f8efdbe73 Merge nommu branch 2006-07-01 20:43:57 +01:00
Russell King
8799ee9f49 [ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the
cache when written to".  On others, this bit is required to
be one, and others it's required to be zero.  Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.

With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-29 18:24:21 +01:00
Russell King
22b1908610 [ARM] nommu: provide a way for correct control register value selection
Most MMU-based CPUs have a restriction on the setting of the data cache
enable and mmu enable bits in the control register, whereby if the data
cache is enabled, the MMU must also be enabled.  Enabling the data
cache without the MMU is an invalid combination.

However, there are CPUs where the data cache can be enabled without the
MMU.

In order to allow these CPUs to take advantage of that, provide a
method whereby each proc-*.S file defines the control regsiter value
for use with nommu (with the MMU disabled.)  Later on, when we add
support for enabling the MMU on these devices, we can adjust the
"crval" macro to also enable the data cache for nommu.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-29 15:09:57 +01:00
Hyok S. Choi
d090dddaba [ARM] nommu: Initial uCLinux support for MMU-based CPUs
In noMMU mode, various of functions which are defined in mm/proc-*.S
is not valid or needed to be avoided. i.g. switch_mm is not needed,
just returns and this makes the I & D caches are valid which shows
great improvement of performance including task switching and IPC.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-28 17:59:56 +01:00
Russell King
800d8b5c4b [ARM] Remove partial non-v6 binutils compatibility
proc-v6 contains some compatibility to be able to use the V6
"cps" instruction.  However, the kernel makes use of this
instruction elsewhere extensively, so there's no point keeping
this compatibility anymore.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-25 11:31:22 +01:00
Russell King
3747b36eea [ARM] proc-v6: mark page table walks outer-cacheable, shared. Enable NX.
Mark page table walks with outer-cacheable attribute, and enable no-execute
in page tables.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-27 16:59:07 +01:00
Russell King
74945c8616 [ARM] nommu: Move hardware page table definitions to pgtable-hwdef.h
Move the hardware PMD and PTE page table definitions from pgtable.h
into pgtable-hwdef.h, and include pgtable-hwdef.h as necessary.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-21 22:03:25 +00:00
Russell King
862184fe01 [ARM SMP] Add Realview MPcore SMP support
Add SMP support for the MPcore tile fitted to the Realview ARM
platform.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-07 21:05:42 +00:00
Russell King
cd03adb081 [ARM SMP] Add support for shared memory attribute
We need to set the shared memory attribute in the page tables
on SMP systems to allow the cache coherency to operate.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-07 10:10:28 +00:00
Tony Lindgren
67c5587ad4 [ARM] 3024/1: Add cpu_v6_proc_fin
Patch from Tony Lindgren

Machine restart calls cpu_proc_fin() to clean and disable
cache, and turn off interrupts. This patch adds proper
cpu_v6_proc_fin.

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-19 23:00:56 +01:00
Ben Dooks
02b7dd1244 [ARM] 2926/1: .proc.info - postfix section with .init for make buildcheck
Patch from Ben Dooks

The `make buildcheck` is erroneously reporting that the .proc.info
list is referencing items in the .init section as it is not itself
postfixed with .init

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-09-20 16:35:03 +01:00
Sam Ravnborg
e6ae744dd2 kbuild: arm - use generic asm-offsets.h support
Delete obsoleted stuff from arch Makefile and rename
constants.h to asm-offsets.h

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
2005-09-09 21:08:59 +02:00
Russell King
d93742f5a7 [ARM] Remove extraneous whitespace introduced in previous ARMv6 patch
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-08-15 16:53:38 +01:00
Russell King
6626a7076d [ARM] Control v6 'global' bit via Linux PTE entries
Unfortunately, we can't use the "user" bit in the page tables to
control whether a page table entry is "global" or "asid" specific,
since the vector page is mapped as "user" accessible but is not
process specific.

Therefore, give direct control of the ARMv6 "nG" (not global)
bit to the mm layers.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-08-10 16:18:35 +01:00
Russell King
1b9749e7f1 [ARM] Use #defined constants for manipulating v6 hardware PTE bits
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-08-10 16:15:32 +01:00
Catalin Marinas
d1d890edac [PATCH] ARM: 2789/1: Enable access to both CP10 and CP11 on ARMv6
Patch from Catalin Marinas

The VFP instructions trigger undefined exceptions because the access to
CP11 is disabled (only CP10 is currently enabled by the kernel). The patch
fixes this problem.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-07-06 23:06:03 +01:00
Catalin Marinas
79042f087b [PATCH] ARM: 2698/1: Enable kernel r/w access to user pages on ARMv6
Patch from Catalin Marinas

cpu_v6_set_pte() sets the kernel access rights to r/o for user
pages (L_PTE_USER) when neither L_PTE_WRITE nor L_PTE_DIRTY are
set. This causes a kernel data abort when writing the TLS value
in the 0xffff0000 page. This patch enables the kernel r/w access.

Signed-off-by: Catalin Marinas
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-06-24 21:27:39 +01:00
Linus Torvalds
1da177e4c3 Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!
2005-04-16 15:20:36 -07:00