Commit graph

18 commits

Author SHA1 Message Date
Yoichi Yuasa
9aa4cc11b2 [MIPS] Cobalt: Fix IRQ comment; the Cobalt kernel uses CP0 counter now.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:48 +00:00
Yoichi Yuasa
3282bd3cb0 [MIPS] Cobalt: Move reset port definition to arch/mips/cobalt/reset.c
It's only used in arch/mips/cobalt/reset.c.

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 23:46:14 +01:00
Yoichi Yuasa
5a860424a1 [MIPS] Cobalt: Move UART base definition to arch/mips/cobalt/console.c
They're only used in arch/mips/cobalt/console.c.

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 23:46:14 +01:00
Yoichi Yuasa
b4126e8630 [MIPS] Cobalt: Move PCI definitions to arch/mips/pci/fixup-cobalt.c.
These PCI definitions are only used in arch/mips/pci/fixup-cobalt.c.

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 23:46:14 +01:00
Ralf Baechle
baf22c1e7a [MIPS] Split up war.h
It was getting a little big, ugly and a primary source for merge conflicts.
Also the old method was a bit too forgiving in that the workaround did
default to off, so now there is an explicit #error forcing platform
maintainers to think if they should enable a workaround for a particular
platform.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 23:46:07 +01:00
Ralf Baechle
641e97f318 [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.
It may not be perfect yet but the SB1 code is badly borken and has
horrible performance issues.

Downside: This seriously breaks support for pass 1 parts of the BCM1250
where indexed cacheops don't work quite reliable but I seem to be the
last one on the planet with a pass 1 part anyway.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 23:46:05 +01:00
Yoichi Yuasa
d5ab1a6910 [MIPS] Add GT641xx IRQ routines.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 23:46:04 +01:00
Ralf Baechle
ed203dadcd [MIPS] Disable UserLocal runtime detection on platforms which never have it.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-20 18:57:39 +01:00
Ralf Baechle
798d9023e4 [MIPS] Disable MT runtime detection on platforms which never support MT.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-20 18:57:39 +01:00
Yoichi Yuasa
e934c82657 [MIPS] remove unused definitions for Cobalt
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10 17:32:55 +01:00
Yoichi Yuasa
44320f2bcb [MIPS] Add extern cobalt_board_id
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-05-11 14:28:32 +01:00
Atsushi Nemoto
97dcb82de6 [MIPS] Define MIPS_CPU_IRQ_BASE in generic header
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259).  Define them in asm-mips/mach-generic/irq.h and make
them customizable.  This will save a few cycle on each CPU interrupt.

A good side effect is removing some dependencies to MALTA in generic
SMTC code.

Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it.  So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.

Testing this patch on those platforms is greatly appreciated.  Thank
you.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-06 16:53:08 +00:00
Yoichi Yuasa
56ae583330 [MIPS] Rewrite GALILEO_INL/GALILEO_OUTL to GT_READ/GT_WRITE
This patch has rewritten GALILEO_INL/GALILEO_OUTL using GT_READ/GT_WRITE.
This patch tested on Cobalt Qube2.

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-11-30 01:14:43 +00:00
Ralf Baechle
fc5d2d279f [MIPS] Use the proper technical term for naming some of the cache macros.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13 21:26:04 +01:00
David Woodhouse
62c4f0a2d5 Don't include linux/config.h from anywhere else in include/
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2006-04-26 12:56:16 +01:00
Peter Horton
e87dddeb92 [MIPS] Add early console for Cobalt.
Signed-off-by: Peter Horton <pdh@colonel-panic.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-21 13:27:44 +00:00
Ralf Baechle
c011db451b [MIPS] CPU definitions for Cobalt.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07 13:30:22 +00:00
Ralf Baechle
11ed6d5bb0 [MIPS] Rename include/asm-mips/cobalt to include/asm-mips/mach-cobalt.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07 13:30:22 +00:00