298 lines
8.7 KiB
C
298 lines
8.7 KiB
C
/*
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* s2mu005-irq.c - Interrupt controller support for s2mu005
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*
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* Copyright (C) 2015 Samsung Electronics Co.Ltd
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* This driver is based on s2mu005-irq.c
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*/
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#include <linux/err.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/gpio.h>
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#include <linux/mfd/samsung/s2mu005.h>
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#include <linux/mfd/samsung/s2mu005-private.h>
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//#include <plat/gpio-cfg.h>
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static const u8 s2mu005_mask_reg[] = {
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/* TODO: Need to check other INTMASK */
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[CHG_INT] = S2MU005_REG_SC_INT_MASK,
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[FLED_INT] = S2MU005_REG_FLED_INT_MASK,
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[MUIC_INT1] = S2MU005_REG_MUIC_INT1_MASK,
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[MUIC_INT2] = S2MU005_REG_MUIC_INT2_MASK,
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};
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struct s2mu005_irq_data {
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int mask;
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enum s2mu005_irq_source group;
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};
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#define DECLARE_IRQ(idx, _group, _mask) \
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[(idx)] = { .group = (_group), .mask = (_mask) }
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static const struct s2mu005_irq_data s2mu005_irqs[] = {
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DECLARE_IRQ(S2MU005_CHG_IRQ_DET_BAT, CHG_INT, 1 << 0),
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DECLARE_IRQ(S2MU005_CHG_IRQ_BAT, CHG_INT, 1 << 1),
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DECLARE_IRQ(S2MU005_CHG_IRQ_IVR, CHG_INT, 1 << 2),
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DECLARE_IRQ(S2MU005_CHG_IRQ_EVENT, CHG_INT, 1 << 3),
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DECLARE_IRQ(S2MU005_CHG_IRQ_CHG, CHG_INT, 1 << 4),
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DECLARE_IRQ(S2MU005_CHG_IRQ_VMID, CHG_INT, 1 << 5),
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DECLARE_IRQ(S2MU005_CHG_IRQ_WCIN, CHG_INT, 1 << 6),
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DECLARE_IRQ(S2MU005_CHG_IRQ_VBUS, CHG_INT, 1 << 7),
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DECLARE_IRQ(S2MU005_FLED_IRQ_LBPROT, FLED_INT, 1 << 2),
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DECLARE_IRQ(S2MU005_FLED_IRQ_OPEN_CH2, FLED_INT, 1 << 4),
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DECLARE_IRQ(S2MU005_FLED_IRQ_OPEN_CH1, FLED_INT, 1 << 5),
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DECLARE_IRQ(S2MU005_FLED_IRQ_SHORT_CH2, FLED_INT, 1 << 6),
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DECLARE_IRQ(S2MU005_FLED_IRQ_SHORT_CH1, FLED_INT, 1 << 7),
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DECLARE_IRQ(S2MU005_MUIC_IRQ1_ATTATCH, MUIC_INT1, 1 << 0),
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DECLARE_IRQ(S2MU005_MUIC_IRQ1_DETACH, MUIC_INT1, 1 << 1),
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DECLARE_IRQ(S2MU005_MUIC_IRQ1_KP, MUIC_INT1, 1 << 2),
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DECLARE_IRQ(S2MU005_MUIC_IRQ1_LKP, MUIC_INT1, 1 << 3),
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DECLARE_IRQ(S2MU005_MUIC_IRQ1_LKR, MUIC_INT1, 1 << 4),
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DECLARE_IRQ(S2MU005_MUIC_IRQ1_RID_CHG, MUIC_INT1, 1 << 5),
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DECLARE_IRQ(S2MU005_MUIC_IRQ2_VBUS_ON, MUIC_INT2, 1 << 0),
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DECLARE_IRQ(S2MU005_MUIC_IRQ2_RSVD_ATTACH, MUIC_INT2, 1 << 1),
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DECLARE_IRQ(S2MU005_MUIC_IRQ2_ADC_CHANGE, MUIC_INT2, 1 << 2),
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DECLARE_IRQ(S2MU005_MUIC_IRQ2_STUCK, MUIC_INT2, 1 << 3),
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DECLARE_IRQ(S2MU005_MUIC_IRQ2_STUCKRCV, MUIC_INT2, 1 << 4),
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DECLARE_IRQ(S2MU005_MUIC_IRQ2_MHDL, MUIC_INT2, 1 << 5),
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DECLARE_IRQ(S2MU005_MUIC_IRQ2_AV_CHARGE, MUIC_INT2, 1 << 6),
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DECLARE_IRQ(S2MU005_MUIC_IRQ2_VBUS_OFF, MUIC_INT2, 1 << 7),
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};
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static void s2mu005_irq_lock(struct irq_data *data)
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{
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struct s2mu005_dev *s2mu005 = irq_get_chip_data(data->irq);
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mutex_lock(&s2mu005->irqlock);
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}
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static void s2mu005_irq_sync_unlock(struct irq_data *data)
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{
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struct s2mu005_dev *s2mu005 = irq_get_chip_data(data->irq);
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int i;
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for (i = 0; i < S2MU005_IRQ_GROUP_NR; i++) {
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u8 mask_reg = s2mu005_mask_reg[i];
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struct i2c_client *i2c = s2mu005->i2c;
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if (mask_reg == S2MU005_REG_INVALID ||
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IS_ERR_OR_NULL(i2c))
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continue;
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s2mu005->irq_masks_cache[i] = s2mu005->irq_masks_cur[i];
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s2mu005_write_reg(i2c, s2mu005_mask_reg[i],
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s2mu005->irq_masks_cur[i]);
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}
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mutex_unlock(&s2mu005->irqlock);
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}
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static const inline struct s2mu005_irq_data *
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irq_to_s2mu005_irq(struct s2mu005_dev *s2mu005, int irq)
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{
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return &s2mu005_irqs[irq - s2mu005->irq_base];
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}
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static void s2mu005_irq_mask(struct irq_data *data)
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{
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struct s2mu005_dev *s2mu005 = irq_get_chip_data(data->irq);
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const struct s2mu005_irq_data *irq_data =
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irq_to_s2mu005_irq(s2mu005, data->irq);
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if (irq_data->group >= S2MU005_IRQ_GROUP_NR)
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return;
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s2mu005->irq_masks_cur[irq_data->group] |= irq_data->mask;
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}
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static void s2mu005_irq_unmask(struct irq_data *data)
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{
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struct s2mu005_dev *s2mu005 = irq_get_chip_data(data->irq);
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const struct s2mu005_irq_data *irq_data =
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irq_to_s2mu005_irq(s2mu005, data->irq);
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if (irq_data->group >= S2MU005_IRQ_GROUP_NR)
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return;
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s2mu005->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
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}
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static struct irq_chip s2mu005_irq_chip = {
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.name = MFD_DEV_NAME,
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.irq_bus_lock = s2mu005_irq_lock,
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.irq_bus_sync_unlock = s2mu005_irq_sync_unlock,
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.irq_mask = s2mu005_irq_mask,
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.irq_unmask = s2mu005_irq_unmask,
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};
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static irqreturn_t s2mu005_irq_thread(int irq, void *data)
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{
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struct s2mu005_dev *s2mu005 = data;
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u8 irq_reg[S2MU005_IRQ_GROUP_NR] = {0};
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// u8 tmp_irq_reg[S2MU005_IRQ_GROUP_NR] = {};
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int i, ret;
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u8 temp, temp_2;
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pr_debug("%s: irq gpio pre-state(0x%02x)\n", __func__,
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gpio_get_value(s2mu005->irq_gpio));
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/* CHG_INT */
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ret = s2mu005_read_reg(s2mu005->i2c, S2MU005_REG_SC_INT,
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&irq_reg[CHG_INT]);
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pr_info("%s: charger interrupt(0x%02x)\n",
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__func__, irq_reg[CHG_INT]);
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/* FLED_INT */
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ret = s2mu005_read_reg(s2mu005->i2c, S2MU005_REG_FLED_INT,
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&irq_reg[FLED_INT]);
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pr_info("%s: fled interrupt(0x%02x)\n", __func__, irq_reg[FLED_INT]);
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/* MUIC INT1 ~ INT2 */
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ret = s2mu005_bulk_read(s2mu005->i2c, S2MU005_REG_MUIC_INT1,
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S2MU005_NUM_IRQ_MUIC_REGS, &irq_reg[MUIC_INT1]);
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pr_info("%s: muic interrupt(0x%02x, 0x%02x)\n", __func__,
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irq_reg[MUIC_INT1], irq_reg[MUIC_INT2]);
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if(s2mu005->pmic_rev == 0) {
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s2mu005_read_reg(s2mu005->i2c, S2MU005_REG_MUIC_ADC, &temp);
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temp &= 0x1F;
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s2mu005_read_reg(s2mu005->i2c, 0x51, &temp_2); /* checking VBUS_WAKEUP bit of R(0x51) */
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if((temp_2 & 0x02) && (temp != 0x18)
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&& (temp != 0x19) && (temp != 0x1C) && (temp != 0x1D) )
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s2mu005_update_reg(s2mu005->i2c, 0x89, 0x01, 0x03);
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if(irq_reg[MUIC_INT2] & 0x80)
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s2mu005_update_reg(s2mu005->i2c, 0x89, 0x03, 0x03);
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}
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/* For OTGGTEST : VMID_INT */
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if (irq_reg[CHG_INT] == 0x20)
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{
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pr_info("%s: VMID_INT\n", __func__);
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irq_reg[MUIC_INT2] |= 0x01;
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}
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/* Apply masking */
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for (i = 0; i < S2MU005_IRQ_GROUP_NR; i++) {
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irq_reg[i] &= ~s2mu005->irq_masks_cur[i];
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}
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/* Report */
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for (i = 0; i < S2MU005_IRQ_NR; i++) {
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if (irq_reg[s2mu005_irqs[i].group] & s2mu005_irqs[i].mask)
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handle_nested_irq(s2mu005->irq_base + i);
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}
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return IRQ_HANDLED;
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}
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int s2mu005_irq_init(struct s2mu005_dev *s2mu005)
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{
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int i;
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int ret;
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struct i2c_client *i2c = s2mu005->i2c;
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struct pinctrl *pinctrl;
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struct pinctrl_state *set_state_i2c;
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if (!s2mu005->irq_gpio) {
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dev_warn(s2mu005->dev, "No interrupt specified.\n");
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s2mu005->irq_base = 0;
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return 0;
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}
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if (!s2mu005->irq_base) {
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dev_err(s2mu005->dev, "No interrupt base specified.\n");
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return 0;
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}
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mutex_init(&s2mu005->irqlock);
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s2mu005->irq = gpio_to_irq(s2mu005->irq_gpio);
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pr_info("%s:%s irq=%d, irq->gpio=%d\n", MFD_DEV_NAME, __func__,
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s2mu005->irq, s2mu005->irq_gpio);
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ret = gpio_request(s2mu005->irq_gpio, "if_pmic_irq");
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if (ret) {
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dev_err(s2mu005->dev, "%s: failed requesting gpio %d\n",
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__func__, s2mu005->irq_gpio);
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return ret;
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}
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gpio_direction_input(s2mu005->irq_gpio);
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gpio_free(s2mu005->irq_gpio);
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/* Get pinctrl if target uses pinctrl */
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printk("[s2mu005] pinctrl!\n");
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pinctrl = devm_pinctrl_get(&s2mu005->i2c->dev);
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if (pinctrl) {
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set_state_i2c = pinctrl_lookup_state(pinctrl, "s2mu005_interrupt_pins_default");
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ret = pinctrl_select_state(pinctrl, set_state_i2c);
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if (ret)
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pr_err("%s: cannot set pinctrl state\n", __func__);
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}else{
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printk("[S2MU005] pinctrl error\n");
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}
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/* Mask individual interrupt sources */
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for (i = 0; i < S2MU005_IRQ_GROUP_NR; i++) {
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s2mu005->irq_masks_cur[i] = 0xff;
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s2mu005->irq_masks_cache[i] = 0xff;
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if (IS_ERR_OR_NULL(i2c))
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continue;
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if (s2mu005_mask_reg[i] == S2MU005_REG_INVALID)
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continue;
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s2mu005_write_reg(i2c, s2mu005_mask_reg[i], 0xff);
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}
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/* Register with genirq */
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for (i = 0; i < S2MU005_IRQ_NR; i++) {
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int cur_irq;
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cur_irq = i + s2mu005->irq_base;
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irq_set_chip_data(cur_irq, s2mu005);
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irq_set_chip_and_handler(cur_irq, &s2mu005_irq_chip,
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handle_level_irq);
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irq_set_nested_thread(cur_irq, 1);
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#ifdef CONFIG_ARM
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set_irq_flags(cur_irq, IRQF_VALID);
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#else
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irq_set_noprobe(cur_irq);
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#endif
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}
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ret = request_threaded_irq(s2mu005->irq, NULL, s2mu005_irq_thread,
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IRQF_TRIGGER_LOW | IRQF_ONESHOT,
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"s2mu005-irq", s2mu005);
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if (ret) {
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dev_err(s2mu005->dev, "Failed to request IRQ %d: %d\n",
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s2mu005->irq, ret);
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return ret;
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}
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return 0;
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}
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void s2mu005_irq_exit(struct s2mu005_dev *s2mu005)
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{
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if (s2mu005->irq)
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free_irq(s2mu005->irq, s2mu005);
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}
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