325 lines
9.3 KiB
C
325 lines
9.3 KiB
C
/*
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* sm5705-irq.c - Interrupt controller support for sm5705
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* This driver is based on sm5705-irq.c
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*/
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#include <linux/err.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/gpio.h>
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#include <linux/mfd/sm5705/sm5705.h>
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//#include <plat/gpio-cfg.h>
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#define SM5705_IRQ_OFFSET_NR 4
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static const u8 sm5705_mask_reg[] = {
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SM5705_REG_INTMSK1,
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SM5705_REG_INTMSK2,
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SM5705_REG_INTMSK3,
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SM5705_REG_INTMSK4,
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};
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enum SM5705_IRQ_OFFSET {
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SM5705_INT1_OFFSET = 0,
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SM5705_INT2_OFFSET,
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SM5705_INT3_OFFSET,
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SM5705_INT4_OFFSET,
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};
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struct sm5705_irq_data {
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int mask;
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int offset;
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};
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#define DECLARE_IRQ(idx, _offset, _mask) \
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[(idx)] = { .offset = (_offset), .mask = (_mask) }
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static const struct sm5705_irq_data sm5705_irqs[] = {
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DECLARE_IRQ(SM5705_VBUSPOK_IRQ, SM5705_INT1_OFFSET, 1 << 0),
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DECLARE_IRQ(SM5705_VBUSUVLO_IRQ, SM5705_INT1_OFFSET, 1 << 1),
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DECLARE_IRQ(SM5705_VBUSOVP_IRQ, SM5705_INT1_OFFSET, 1 << 2),
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DECLARE_IRQ(SM5705_VBUSLIMIT_IRQ, SM5705_INT1_OFFSET, 1 << 3),
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DECLARE_IRQ(SM5705_WPCINPOK_IRQ, SM5705_INT1_OFFSET, 1 << 4),
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DECLARE_IRQ(SM5705_WPCINUVLO_IRQ, SM5705_INT1_OFFSET, 1 << 5),
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DECLARE_IRQ(SM5705_WPCINOVP_IRQ, SM5705_INT1_OFFSET, 1 << 6),
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DECLARE_IRQ(SM5705_WPCINLIMIT_IRQ, SM5705_INT1_OFFSET, 1 << 7),
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DECLARE_IRQ(SM5705_AICL_IRQ, SM5705_INT2_OFFSET, 1 << 0),
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DECLARE_IRQ(SM5705_BATOVP_IRQ, SM5705_INT2_OFFSET, 1 << 1),
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DECLARE_IRQ(SM5705_NOBAT_IRQ, SM5705_INT2_OFFSET, 1 << 2),
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DECLARE_IRQ(SM5705_CHGON_IRQ, SM5705_INT2_OFFSET, 1 << 3),
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DECLARE_IRQ(SM5705_Q4FULLON_IRQ, SM5705_INT2_OFFSET, 1 << 4),
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DECLARE_IRQ(SM5705_TOPOFF_IRQ, SM5705_INT2_OFFSET, 1 << 5),
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DECLARE_IRQ(SM5705_DONE_IRQ, SM5705_INT2_OFFSET, 1 << 6),
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DECLARE_IRQ(SM5705_WDTMROFF_IRQ, SM5705_INT2_OFFSET, 1 << 7),
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DECLARE_IRQ(SM5705_THEMREG_IRQ, SM5705_INT3_OFFSET, 1 << 0),
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DECLARE_IRQ(SM5705_THEMSHDN_IRQ, SM5705_INT3_OFFSET, 1 << 1),
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DECLARE_IRQ(SM5705_OTGFAIL_IRQ, SM5705_INT3_OFFSET, 1 << 2),
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DECLARE_IRQ(SM5705_DISLIMIT_IRQ, SM5705_INT3_OFFSET, 1 << 3),
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DECLARE_IRQ(SM5705_PRETMROFF_IRQ, SM5705_INT3_OFFSET, 1 << 4),
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DECLARE_IRQ(SM5705_FASTTMROFF_IRQ, SM5705_INT3_OFFSET, 1 << 5),
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DECLARE_IRQ(SM5705_LOWBATT_IRQ, SM5705_INT3_OFFSET, 1 << 6),
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DECLARE_IRQ(SM5705_nENQ4_IRQ, SM5705_INT3_OFFSET, 1 << 7),
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DECLARE_IRQ(SM5705_FLED1SHORT_IRQ, SM5705_INT4_OFFSET, 1 << 0),
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DECLARE_IRQ(SM5705_FLED1OPEN_IRQ, SM5705_INT4_OFFSET, 1 << 1),
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DECLARE_IRQ(SM5705_FLED2SHORT_IRQ, SM5705_INT4_OFFSET, 1 << 2),
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DECLARE_IRQ(SM5705_FLED2OPEN_IRQ, SM5705_INT4_OFFSET, 1 << 3),
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DECLARE_IRQ(SM5705_BOOSTPOK_NG_IRQ, SM5705_INT4_OFFSET, 1 << 4),
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DECLARE_IRQ(SM5705_BOOSTPOK_IRQ, SM5705_INT4_OFFSET, 1 << 5),
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DECLARE_IRQ(SM5705_ABSTMR1OFF_IRQ, SM5705_INT4_OFFSET, 1 << 6),
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DECLARE_IRQ(SM5705_SBPS_IRQ, SM5705_INT4_OFFSET, 1 << 7),
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};
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static void sm5705_irq_lock(struct irq_data *data)
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{
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struct sm5705_dev *sm5705 = irq_get_chip_data(data->irq);
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mutex_lock(&sm5705->irqlock);
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}
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static void sm5705_irq_sync_unlock(struct irq_data *data)
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{
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struct sm5705_dev *sm5705 = irq_get_chip_data(data->irq);
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int i;
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for (i = 0; i < SM5705_IRQ_OFFSET_NR; i++) {
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u8 mask_reg = sm5705_mask_reg[i];
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if (mask_reg == SM5705_REG_INVALID ||
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IS_ERR_OR_NULL(sm5705->i2c))
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continue;
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sm5705->irq_masks_cache[i] = sm5705->irq_masks_cur[i];
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sm5705_write_reg(sm5705->i2c, sm5705_mask_reg[i],
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sm5705->irq_masks_cur[i]);
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}
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mutex_unlock(&sm5705->irqlock);
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}
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static const inline struct sm5705_irq_data *
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irq_to_sm5705_irq(struct sm5705_dev *sm5705, int irq)
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{
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return &sm5705_irqs[irq - sm5705->irq_base];
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}
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static void sm5705_irq_mask(struct irq_data *data)
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{
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struct sm5705_dev *sm5705 = irq_get_chip_data(data->irq);
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const struct sm5705_irq_data *irq_data =
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irq_to_sm5705_irq(sm5705, data->irq);
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sm5705->irq_masks_cur[irq_data->offset] |= irq_data->mask;
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}
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static void sm5705_irq_unmask(struct irq_data *data)
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{
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struct sm5705_dev *sm5705 = irq_get_chip_data(data->irq);
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const struct sm5705_irq_data *irq_data =
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irq_to_sm5705_irq(sm5705, data->irq);
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sm5705->irq_masks_cur[irq_data->offset] &= ~irq_data->mask;
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}
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static struct irq_chip sm5705_irq_chip = {
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.name = MFD_DEV_NAME,
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.irq_bus_lock = sm5705_irq_lock,
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.irq_bus_sync_unlock = sm5705_irq_sync_unlock,
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.irq_mask = sm5705_irq_mask,
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.irq_unmask = sm5705_irq_unmask,
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};
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static int sm5705_read_irq_status(struct sm5705_dev *sm5705)
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{
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int ret;
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struct i2c_client *iic = sm5705->i2c;
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ret = sm5705_read_reg(iic, SM5705_REG_INT1,
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&sm5705->irq_status[0]);
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if (ret < 0) {
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pr_err("Failed on reading irq1 status\n");
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return ret;
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}
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// printk("sm5705 irq1 = 0x%x\n", (int)sm5705->irq_status[0]);
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ret = sm5705_read_reg(iic, SM5705_REG_INT2,
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&sm5705->irq_status[1]);
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if (ret < 0) {
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pr_err("Failed on reading irq2 status\n");
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return ret;
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}
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// printk("sm5705 irq2 = 0x%x\n", (int)sm5705->irq_status[1]);
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ret = sm5705_read_reg(iic, SM5705_REG_INT3,
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&sm5705->irq_status[2]);
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if (ret < 0) {
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pr_err("Failed on reading irq3 status\n");
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return ret;
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}
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// printk("sm5705 irq3 = 0x%x\n", (int)sm5705->irq_status[2]);
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ret = sm5705_read_reg(iic, SM5705_REG_INT4,
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&sm5705->irq_status[3]);
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if (ret < 0) {
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pr_err("Failed on reading irq4 status\n");
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return ret;
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}
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// printk("sm5705 irq4 = 0x%x\n", (int)sm5705->irq_status[3]);
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return 0;
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}
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static irqreturn_t sm5705_irq_thread(int irq, void *data)
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{
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struct sm5705_dev *sm5705 = data;
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int i, ret;
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pr_info("%s: irq gpio pre-state(0x%02x)\n", __func__,
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gpio_get_value(sm5705->irq_gpio));
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ret = sm5705_read_irq_status(sm5705);
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if (ret < 0) {
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pr_err("%s :Error : can't read irq status (%d)\n",
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__func__, ret);
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return ret;
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}
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/* Apply masking */
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for (i = 0; i < SM5705_IRQ_OFFSET_NR; i++) {
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sm5705->irq_status[i] &= ~sm5705->irq_masks_cur[i];
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}
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/* Report */
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for (i = 0; i < SM5705_MAX_IRQ; i++) {
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if (sm5705->irq_status[sm5705_irqs[i].offset] & sm5705_irqs[i].mask)
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handle_nested_irq(sm5705->irq_base + i);
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}
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return IRQ_HANDLED;
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}
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static uint8_t sm5705_irqs_ctrl_mask_all_val[] = {
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0xff,
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0x9a, //DONEM, TOPOFFM, NOBATM, AICLM
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0xff,
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0xff,
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};
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static int sm5705_mask_all_irqs(struct sm5705_dev *sm5705)
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{
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int rc;
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int i;
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for (i=0;i<ARRAY_SIZE(sm5705_mask_reg);i++) {
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rc = sm5705_write_reg(sm5705->i2c, sm5705_mask_reg[i],
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sm5705_irqs_ctrl_mask_all_val[i]);
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sm5705->irq_masks_cache[i] = sm5705_irqs_ctrl_mask_all_val[i];
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if (rc<0) {
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pr_info("Error : can't write reg[0x%x] = 0x%x\n",
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sm5705_mask_reg[i],
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sm5705_irqs_ctrl_mask_all_val[i]);
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return rc;
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}
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}
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return 0;
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}
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int sm5705_irq_init(struct sm5705_dev *sm5705)
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{
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int i;
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int ret;
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ret = sm5705_mask_all_irqs(sm5705);
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if (!sm5705->irq_gpio) {
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dev_warn(sm5705->dev, "No interrupt specified.\n");
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sm5705->irq_base = 0;
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return 0;
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}
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if (!sm5705->irq_base) {
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dev_err(sm5705->dev, "No interrupt base specified.\n");
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return 0;
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}
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mutex_init(&sm5705->irqlock);
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sm5705->irq = gpio_to_irq(sm5705->irq_gpio);
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pr_info("%s:%s irq=%d, irq->gpio=%d\n", MFD_DEV_NAME, __func__,
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sm5705->irq, sm5705->irq_gpio);
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ret = gpio_request(sm5705->irq_gpio, "sm5705_mfd_irq");
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if (ret) {
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dev_err(sm5705->dev, "%s: failed requesting gpio %d\n",
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__func__, sm5705->irq_gpio);
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return ret;
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}
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gpio_direction_input(sm5705->irq_gpio);
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gpio_free(sm5705->irq_gpio);
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/* Mask individual interrupt sources */
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for (i = 0; i < SM5705_IRQ_OFFSET_NR; i++) {
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sm5705->irq_masks_cur[i] = 0xff;
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sm5705->irq_masks_cache[i] = 0xff;
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if (IS_ERR_OR_NULL(sm5705->i2c))
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continue;
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if (sm5705_mask_reg[i] == SM5705_REG_INVALID)
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continue;
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sm5705_write_reg(sm5705->i2c, sm5705_mask_reg[i], 0xff);
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}
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/* Register with genirq */
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for (i = 0; i < SM5705_MAX_IRQ; i++) {
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int cur_irq;
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cur_irq = i + sm5705->irq_base;
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irq_set_chip_data(cur_irq, sm5705);
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irq_set_chip_and_handler(cur_irq, &sm5705_irq_chip,
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handle_level_irq);
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irq_set_nested_thread(cur_irq, 1);
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#ifdef CONFIG_ARM
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set_irq_flags(cur_irq, IRQF_VALID);
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#else
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irq_set_noprobe(cur_irq);
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#endif
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}
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ret = request_threaded_irq(sm5705->irq, NULL, sm5705_irq_thread,
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IRQF_TRIGGER_LOW | IRQF_ONESHOT | IRQF_NO_SUSPEND,
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"sm5705-irq", sm5705);
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if (ret) {
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dev_err(sm5705->dev, "Failed to request IRQ %d: %d\n",
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sm5705->irq, ret);
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return ret;
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}
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return 0;
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}
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void sm5705_irq_exit(struct sm5705_dev *sm5705)
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{
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if (sm5705->irq)
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free_irq(sm5705->irq, sm5705);
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}
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