211 lines
6.6 KiB
C
211 lines
6.6 KiB
C
/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __PINCTRL_MSM_H__
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#define __PINCTRL_MSM_H__
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#include <linux/gpio.h>
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#include <linux/irq.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/platform_device.h>
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#define MSM_PINTYPE_SDC_REGS_MAX 10
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#define MSM_PINTYPE_EBI_REGS_MAX 10
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/**
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* struct msm_pin_group: group of pins having the same pinmux function.
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* @name: name of the pin group.
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* @pins: the pins included in this group.
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* @num_pins: number of pins included in this group.
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* @func: the function number to be programmed when selected.
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*/
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struct msm_pin_grps {
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const char *name;
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unsigned int *pins;
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unsigned num_pins;
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u32 func;
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};
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/**
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* struct msm_pmx_funcs: represent a pin function.
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* @name: name of the pin function.
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* @gps: one or more names of pin groups that provide this function.
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* @num_grps: number of groups included in @groups.
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*/
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struct msm_pmx_funcs {
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const char *name;
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const char **gps;
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unsigned num_grps;
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};
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/**
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* struct msm_tlmm_irq_chip: represents interrupt controller descriptor
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* @irq: irq number for tlmm summary interrupt.
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* @chip_base: base register for TLMM.
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* @num_irqs: number of pins that can be used as irq lines.
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* @apps_id: id assigned to the apps processor.
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* @enabled_irqs: bitmask of pins enabled as interrupts.
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* @wake_irqs: bitmask of pins enabled as wake up interrupts.
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* @irq_lock: protect against concurrent access.
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* @domain: irq domain of given interrupt controller
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* @irq_chip: irq chip operations.
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* @irq_chip_extn: extension of irq chip operations.
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* @dev: TLMM device.
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* @device_node: device tree node of interrupt controller.
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* @pinfo: pintype information.
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* @handler: irq handler for given pintype interrupt controller
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*/
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struct msm_tlmm_irq_chip {
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int irq;
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void *__iomem chip_base;
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unsigned int num_irqs;
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unsigned int apps_id;
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unsigned long *enabled_irqs;
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unsigned long *dual_edge_irqs;
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unsigned long *wake_irqs;
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spinlock_t irq_lock;
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struct irq_domain *domain;
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const struct irq_domain_ops *domain_ops;
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struct irq_chip chip;
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struct irq_chip *irq_chip_extn;
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struct device *dev;
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struct device_node *node;
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void *pinfo;
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irqreturn_t (*handler)(int irq, struct msm_tlmm_irq_chip *ic);
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};
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enum msm_pintype {
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MSM_PINTYPE_GP,
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MSM_PINTYPE_SDC,
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MSM_PINTYPE_QDSD,
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MSM_PINTYPE_EBI,
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MSM_PINTYPE_MAX,
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};
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/**
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* struct msm_pintype_data: contains SoC specific pintype info.
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* @reg_base_offset : current pin type's base register offset.
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* @gp_reg_size : delta between a register to next one for pintype gp.
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* @sdc_reg_offsets : sdc pins' register offset from the base address in array.
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* offset array consists of
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* [SDC1 CLK, SDC1 CMD, SDC1 DATA, SDC1 RCLK,
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* SDC2 CLK, SDC2 CMD, SDC2 DATA,
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* SDC3 CLK, SDC3 CMD, SDC3 DATA]
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* @ebi_reg_offsets : ebi pins' register offset from the base address in array.
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* offset array consists of
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* [EBI2 CS, EBI2 OE, EBI2 ALE,
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* EBI2 CLE, EBI2 WE, EBI2 BUSY, EBI2 DATA]
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*/
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struct msm_pintype_data {
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unsigned long reg_base_offset;
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union {
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u32 gp_reg_size;
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s32 sdc_reg_offsets[MSM_PINTYPE_SDC_REGS_MAX];
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s32 ebi_reg_offsets[MSM_PINTYPE_EBI_REGS_MAX];
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};
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};
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/**
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* struct msm_pintype_info: represent a pin type supported by the TLMM.
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* @prg_cfg: helper to program a given config for a pintype.
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* @prg_func: helper to program a given func for a pintype.
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* @pack_cfg: helper to pack a parsed config as per a pintype.
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* @set_reg_base: helper to set the register base address for a pintype.
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* @init_irq: helper to initialize any irq functionality.
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* @reg_data: register base for a pintype.
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* @prop_name: DT property name for a pintype.
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* @name: name of pintype.
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* @num_pins: number of pins of given pintype.
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* @pin_start: starting pin number for the given pintype within pinctroller.
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* @pin_end: ending pin number for the given pintype within pinctroller.
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* @gc: gpio chip implementation for pin type.
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* @irq_chip: interrupt controller support for given pintype.
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* @supports_gpio: pintype supports gpio function.
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* @grange: pins that map to gpios.
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* @node: device node for the pintype.
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* @pintype_data: SoC specific pintype data.
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*/
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struct msm_pintype_info {
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int (*prg_cfg)(uint pin_no, unsigned long *config,
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bool rw, const struct msm_pintype_info *pinfo);
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void (*prg_func)(uint pin_no, u32 func, bool enable,
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const struct msm_pintype_info *pinfo);
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int (*init_irq)(int irq, struct msm_pintype_info *pinfo,
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struct device *tlmm_dev);
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void (*set_reg_base)(void __iomem *tlmm_base,
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struct msm_pintype_info *pinfo);
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void __iomem *reg_base;
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const char *name;
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u32 num_pins;
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int pin_start;
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int pin_end;
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struct gpio_chip gc;
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struct msm_tlmm_irq_chip *irq_chip;
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bool supports_gpio;
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struct pinctrl_gpio_range grange;
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struct device_node *node;
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const struct msm_pintype_data *pintype_data;
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};
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/**
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* struct msm_tlmm_pintype: represents all the TLMM pintypes for a given TLMM
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* version.
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* @num_entries: number of pintypes.
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* @pintype_info: descriptor for the pintypes. One for each present.
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*/
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struct msm_tlmm_pintype {
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const uint num_entries;
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struct msm_pintype_info *pintype_info;
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};
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/**
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* struct msm_pindesc: descriptor for all pins maintained by pinctrl driver
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* @pin_info: pintype for a given pin.
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* @name: name of the pin.
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*/
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struct msm_pindesc {
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struct msm_pintype_info *pin_info;
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char name[20];
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};
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/**
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* struct msm_tlmm_desc: descriptor for the TLMM hardware block
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* @base: base address of tlmm desc.
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* @irq: summary irq number for tlmm block. Must be > 0 if present.
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* @num_pintypes: Number of pintypes on the tlmm block for a given SOC.
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* @pintypes: pintypes supported on a given TLMM block for a given SOC.
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*/
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struct msm_tlmm_desc {
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void __iomem *base;
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int irq;
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unsigned int num_pintypes;
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struct msm_pintype_info *pintypes;
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};
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/* Common probe for all TLMM */
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int msm_pinctrl_probe(struct platform_device *pdev,
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struct msm_tlmm_desc *tlmm_info);
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#ifdef CONFIG_USE_PINCTRL_IRQ
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#ifdef CONFIG_PINCTRL_MSM_TLMM
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extern int msm_tlmm_of_gp_irq_init(struct device_node *np, struct irq_chip *ic);
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#else
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static inline int msm_tlmm_of_gp_irq_init(struct device_node *np,
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struct irq_chip *ic)
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{
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return -EIO;
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}
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#endif
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#endif
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#endif
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