734 lines
19 KiB
C
734 lines
19 KiB
C
/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/slab.h>
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#include <linux/spmi.h>
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#include <linux/string.h>
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#include <linux/regulator/driver.h>
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#include <linux/regulator/machine.h>
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#include <linux/regulator/of_regulator.h>
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#include <linux/regulator/spm-regulator.h>
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#include <soc/qcom/spm.h>
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#define SPM_REGULATOR_DRIVER_NAME "qcom,spm-regulator"
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struct voltage_range {
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int min_uV;
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int set_point_min_uV;
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int max_uV;
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int step_uV;
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};
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enum qpnp_regulator_uniq_type {
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QPNP_TYPE_FTS2,
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QPNP_TYPE_FTS2p5,
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QPNP_TYPE_ULT_HF,
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};
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enum qpnp_regulator_type {
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QPNP_FTS2_TYPE = 0x1C,
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QPNP_FTS2p5_TYPE = 0x1C,
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QPNP_ULT_HF_TYPE = 0x22,
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};
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enum qpnp_regulator_subtype {
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QPNP_FTS2_SUBTYPE = 0x08,
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QPNP_FTS2p5_SUBTYPE = 0x09,
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QPNP_ULT_HF_SUBTYPE = 0x0D,
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};
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static const struct voltage_range fts2_range0 = {0, 350000, 1275000, 5000};
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static const struct voltage_range fts2_range1 = {0, 700000, 2040000, 10000};
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static const struct voltage_range fts2p5_range0
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= { 80000, 350000, 1355000, 5000};
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static const struct voltage_range fts2p5_range1
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= {160000, 700000, 2200000, 10000};
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static const struct voltage_range ult_hf_range0 = {375000, 375000, 1562500,
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12500};
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static const struct voltage_range ult_hf_range1 = {750000, 750000, 1525000,
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25000};
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#define QPNP_SMPS_REG_TYPE 0x04
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#define QPNP_SMPS_REG_SUBTYPE 0x05
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#define QPNP_FTS2_REG_VOLTAGE_RANGE 0x40
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#define QPNP_SMPS_REG_VOLTAGE_SETPOINT 0x41
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#define QPNP_SMPS_REG_MODE 0x45
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#define QPNP_SMPS_REG_STEP_CTRL 0x61
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#define QPNP_SMPS_MODE_PWM 0x80
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#define QPNP_FTS2_MODE_AUTO 0x40
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#define QPNP_FTS2_STEP_CTRL_STEP_MASK 0x18
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#define QPNP_FTS2_STEP_CTRL_STEP_SHIFT 3
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#define QPNP_SMPS_STEP_CTRL_DELAY_MASK 0x07
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#define QPNP_SMPS_STEP_CTRL_DELAY_SHIFT 0
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/* Clock rate in kHz of the FTS2 regulator reference clock. */
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#define QPNP_FTS2_CLOCK_RATE 19200
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/* Time to delay in us to ensure that a mode change has completed. */
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#define QPNP_FTS2_MODE_CHANGE_DELAY 50
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/* Minimum time in us that it takes to complete a single SPMI write. */
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#define QPNP_SPMI_WRITE_MIN_DELAY 8
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/* Minimum voltage stepper delay for each step. */
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#define QPNP_FTS2_STEP_DELAY 8
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#define QPNP_ULT_HF_STEP_DELAY 20
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/*
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* The ratio QPNP_FTS2_STEP_MARGIN_NUM/QPNP_FTS2_STEP_MARGIN_DEN is use to
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* adjust the step rate in order to account for oscillator variance.
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*/
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#define QPNP_FTS2_STEP_MARGIN_NUM 4
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#define QPNP_FTS2_STEP_MARGIN_DEN 5
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/*
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* Settling delay for FTS2.5
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* Warm-up=20uS, 0-10% & 90-100% non-linear V-ramp delay = 50uS
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*/
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#define FTS2P5_SETTLING_DELAY_US 70
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/* VSET value to decide the range of ULT SMPS */
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#define ULT_SMPS_RANGE_SPLIT 0x60
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struct spm_vreg {
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struct regulator_desc rdesc;
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struct regulator_dev *rdev;
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struct spmi_device *spmi_dev;
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const struct voltage_range *range;
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int uV;
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int last_set_uV;
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unsigned vlevel;
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unsigned last_set_vlevel;
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bool online;
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u16 spmi_base_addr;
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u8 init_mode;
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u8 mode;
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int step_rate;
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enum qpnp_regulator_uniq_type regulator_type;
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u32 cpu_num;
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bool bypass_spm;
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};
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static int qpnp_smps_set_mode(struct spm_vreg *vreg, u8 mode)
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{
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int rc;
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rc = spmi_ext_register_writel(vreg->spmi_dev->ctrl, vreg->spmi_dev->sid,
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vreg->spmi_base_addr + QPNP_SMPS_REG_MODE, &mode, 1);
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if (rc)
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dev_err(&vreg->spmi_dev->dev, "%s: could not write to mode register, rc=%d\n",
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__func__, rc);
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return rc;
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}
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static int _spm_regulator_set_voltage(struct regulator_dev *rdev)
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{
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struct spm_vreg *vreg = rdev_get_drvdata(rdev);
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bool spm_failed = false;
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int rc = 0;
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u32 slew_delay;
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u8 reg;
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if (vreg->vlevel == vreg->last_set_vlevel)
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return 0;
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if ((vreg->regulator_type == QPNP_TYPE_FTS2)
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&& !(vreg->init_mode & QPNP_SMPS_MODE_PWM)
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&& vreg->uV > vreg->last_set_uV) {
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/* Switch to PWM mode so that voltage ramping is fast. */
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rc = qpnp_smps_set_mode(vreg, QPNP_SMPS_MODE_PWM);
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if (rc)
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return rc;
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}
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if (likely(!vreg->bypass_spm)) {
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/* Set voltage control register via SPM. */
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rc = msm_spm_set_vdd(vreg->cpu_num, vreg->vlevel);
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if (rc) {
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pr_debug("%s: msm_spm_set_vdd failed, rc=%d; falling back on SPMI write\n",
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vreg->rdesc.name, rc);
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spm_failed = true;
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}
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}
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if (unlikely(vreg->bypass_spm || spm_failed)) {
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/* Set voltage control register via SPMI. */
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reg = vreg->vlevel;
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rc = spmi_ext_register_writel(vreg->spmi_dev->ctrl,
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vreg->spmi_dev->sid,
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vreg->spmi_base_addr + QPNP_SMPS_REG_VOLTAGE_SETPOINT,
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®, 1);
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if (rc) {
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pr_err("%s: spmi_ext_register_writel failed, rc=%d\n",
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vreg->rdesc.name, rc);
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return rc;
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}
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}
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if (vreg->uV > vreg->last_set_uV) {
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/* Wait for voltage stepping to complete. */
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slew_delay = DIV_ROUND_UP(vreg->uV - vreg->last_set_uV,
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vreg->step_rate);
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if (vreg->regulator_type == QPNP_TYPE_FTS2p5)
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slew_delay += FTS2P5_SETTLING_DELAY_US;
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udelay(slew_delay);
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} else if (vreg->regulator_type == QPNP_TYPE_FTS2p5) {
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/* add the ramp-down delay */
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slew_delay = DIV_ROUND_UP(vreg->last_set_uV - vreg->uV,
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vreg->step_rate) + FTS2P5_SETTLING_DELAY_US;
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udelay(slew_delay);
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}
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if ((vreg->regulator_type == QPNP_TYPE_FTS2)
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&& !(vreg->init_mode & QPNP_SMPS_MODE_PWM)
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&& vreg->uV > vreg->last_set_uV) {
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/* Wait for mode transition to complete. */
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udelay(QPNP_FTS2_MODE_CHANGE_DELAY - QPNP_SPMI_WRITE_MIN_DELAY);
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/* Switch to AUTO mode so that power consumption is lowered. */
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rc = qpnp_smps_set_mode(vreg, QPNP_FTS2_MODE_AUTO);
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if (rc)
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return rc;
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}
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vreg->last_set_uV = vreg->uV;
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vreg->last_set_vlevel = vreg->vlevel;
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return rc;
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}
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static int spm_regulator_set_voltage(struct regulator_dev *rdev, int min_uV,
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int max_uV, unsigned *selector)
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{
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struct spm_vreg *vreg = rdev_get_drvdata(rdev);
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const struct voltage_range *range = vreg->range;
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int uV = min_uV;
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unsigned vlevel;
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if (uV < range->set_point_min_uV && max_uV >= range->set_point_min_uV)
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uV = range->set_point_min_uV;
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if (uV < range->set_point_min_uV || uV > range->max_uV) {
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pr_err("%s: request v=[%d, %d] is outside possible v=[%d, %d]\n",
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vreg->rdesc.name, min_uV, max_uV,
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range->set_point_min_uV, range->max_uV);
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return -EINVAL;
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}
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vlevel = DIV_ROUND_UP(uV - range->min_uV, range->step_uV);
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uV = vlevel * range->step_uV + range->min_uV;
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if (uV > max_uV) {
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pr_err("%s: request v=[%d, %d] cannot be met by any set point\n",
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vreg->rdesc.name, min_uV, max_uV);
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return -EINVAL;
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}
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*selector = vlevel -
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(vreg->range->set_point_min_uV - vreg->range->min_uV)
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/ vreg->range->step_uV;
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/* Fix VSET for ULT HF Buck */
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if ((vreg->regulator_type == QPNP_TYPE_ULT_HF) &&
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(range == &ult_hf_range1)) {
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vlevel &= 0x1F;
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vlevel |= ULT_SMPS_RANGE_SPLIT;
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}
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vreg->vlevel = vlevel;
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vreg->uV = uV;
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if (!vreg->online)
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return 0;
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return _spm_regulator_set_voltage(rdev);
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}
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static int spm_regulator_get_voltage(struct regulator_dev *rdev)
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{
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struct spm_vreg *vreg = rdev_get_drvdata(rdev);
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return vreg->uV;
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}
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static int spm_regulator_list_voltage(struct regulator_dev *rdev,
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unsigned selector)
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{
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struct spm_vreg *vreg = rdev_get_drvdata(rdev);
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if (selector >= vreg->rdesc.n_voltages)
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return 0;
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return selector * vreg->range->step_uV + vreg->range->set_point_min_uV;
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}
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static int spm_regulator_enable(struct regulator_dev *rdev)
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{
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struct spm_vreg *vreg = rdev_get_drvdata(rdev);
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int rc;
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rc = _spm_regulator_set_voltage(rdev);
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if (!rc)
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vreg->online = true;
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return rc;
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}
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static int spm_regulator_disable(struct regulator_dev *rdev)
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{
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struct spm_vreg *vreg = rdev_get_drvdata(rdev);
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vreg->online = false;
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return 0;
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}
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static int spm_regulator_is_enabled(struct regulator_dev *rdev)
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{
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struct spm_vreg *vreg = rdev_get_drvdata(rdev);
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return vreg->online;
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}
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static unsigned int spm_regulator_get_mode(struct regulator_dev *rdev)
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{
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struct spm_vreg *vreg = rdev_get_drvdata(rdev);
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return vreg->mode == QPNP_SMPS_MODE_PWM
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? REGULATOR_MODE_NORMAL : REGULATOR_MODE_IDLE;
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}
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static int spm_regulator_set_mode(struct regulator_dev *rdev, unsigned int mode)
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{
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struct spm_vreg *vreg = rdev_get_drvdata(rdev);
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/*
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* Map REGULATOR_MODE_NORMAL to PWM mode and REGULATOR_MODE_IDLE to
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* init_mode. This ensures that the regulator always stays in PWM mode
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* in the case that qcom,mode has been specified as "pwm" in device
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* tree.
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*/
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vreg->mode
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= mode == REGULATOR_MODE_NORMAL ? QPNP_SMPS_MODE_PWM : vreg->init_mode;
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return qpnp_smps_set_mode(vreg, vreg->mode);
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}
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static struct regulator_ops spm_regulator_ops = {
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.get_voltage = spm_regulator_get_voltage,
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.set_voltage = spm_regulator_set_voltage,
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.list_voltage = spm_regulator_list_voltage,
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.get_mode = spm_regulator_get_mode,
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.set_mode = spm_regulator_set_mode,
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.enable = spm_regulator_enable,
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.disable = spm_regulator_disable,
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.is_enabled = spm_regulator_is_enabled,
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};
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static int qpnp_smps_check_type(struct spm_vreg *vreg)
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{
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int rc;
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u8 type[2];
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rc = spmi_ext_register_readl(vreg->spmi_dev->ctrl, vreg->spmi_dev->sid,
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vreg->spmi_base_addr + QPNP_SMPS_REG_TYPE, type, 2);
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if (rc) {
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dev_err(&vreg->spmi_dev->dev, "%s: could not read type register, rc=%d\n",
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__func__, rc);
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return rc;
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}
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if (type[0] == QPNP_FTS2_TYPE && type[1] == QPNP_FTS2_SUBTYPE) {
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vreg->regulator_type = QPNP_TYPE_FTS2;
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} else if (type[0] == QPNP_FTS2p5_TYPE
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&& type[1] == QPNP_FTS2p5_SUBTYPE) {
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vreg->regulator_type = QPNP_TYPE_FTS2p5;
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} else if (type[0] == QPNP_ULT_HF_TYPE
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&& type[1] == QPNP_ULT_HF_SUBTYPE) {
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vreg->regulator_type = QPNP_TYPE_ULT_HF;
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} else {
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dev_err(&vreg->spmi_dev->dev, "%s: invalid type=0x%02X, subtype=0x%02X register pair\n",
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__func__, type[0], type[1]);
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return -ENODEV;
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};
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return rc;
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}
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static int qpnp_fts_init_range(struct spm_vreg *vreg,
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const struct voltage_range *range0, const struct voltage_range *range1)
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{
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int rc;
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u8 reg = 0;
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rc = spmi_ext_register_readl(vreg->spmi_dev->ctrl, vreg->spmi_dev->sid,
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vreg->spmi_base_addr + QPNP_FTS2_REG_VOLTAGE_RANGE, ®, 1);
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if (rc) {
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dev_err(&vreg->spmi_dev->dev, "%s: could not read voltage range register, rc=%d\n",
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__func__, rc);
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return rc;
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}
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if (reg == 0x00) {
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vreg->range = range0;
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} else if (reg == 0x01) {
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vreg->range = range1;
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} else {
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dev_err(&vreg->spmi_dev->dev, "%s: voltage range=%d is invalid\n",
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__func__, reg);
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rc = -EINVAL;
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}
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return rc;
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}
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static int qpnp_ult_hf_init_range(struct spm_vreg *vreg)
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{
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int rc;
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u8 reg = 0;
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rc = spmi_ext_register_readl(vreg->spmi_dev->ctrl, vreg->spmi_dev->sid,
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vreg->spmi_base_addr + QPNP_SMPS_REG_VOLTAGE_SETPOINT, ®, 1);
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if (rc) {
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dev_err(&vreg->spmi_dev->dev, "%s: could not read voltage range register, rc=%d\n",
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__func__, rc);
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return rc;
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}
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vreg->range = (reg < ULT_SMPS_RANGE_SPLIT) ? &ult_hf_range0 :
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&ult_hf_range1;
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return rc;
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}
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static int qpnp_smps_init_voltage(struct spm_vreg *vreg)
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{
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int rc;
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u8 reg = 0;
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rc = spmi_ext_register_readl(vreg->spmi_dev->ctrl, vreg->spmi_dev->sid,
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vreg->spmi_base_addr + QPNP_SMPS_REG_VOLTAGE_SETPOINT, ®, 1);
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if (rc) {
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dev_err(&vreg->spmi_dev->dev, "%s: could not read voltage setpoint register, rc=%d\n",
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__func__, rc);
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return rc;
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}
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vreg->vlevel = reg;
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/*
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* Calculate ULT HF buck VSET based on range:
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* In case of range 0: VSET is a 7 bit value.
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* In case of range 1: VSET is a 5 bit value
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*
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*/
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if ((vreg->regulator_type == QPNP_TYPE_ULT_HF) &&
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(vreg->range == &ult_hf_range1))
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vreg->vlevel &= ~ULT_SMPS_RANGE_SPLIT;
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vreg->uV = vreg->vlevel * vreg->range->step_uV + vreg->range->min_uV;
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vreg->last_set_uV = vreg->uV;
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return rc;
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}
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static int qpnp_smps_init_mode(struct spm_vreg *vreg)
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{
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const char *mode_name;
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int rc;
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rc = of_property_read_string(vreg->spmi_dev->dev.of_node, "qcom,mode",
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&mode_name);
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if (!rc) {
|
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if (strcmp("pwm", mode_name) == 0) {
|
|
vreg->init_mode = QPNP_SMPS_MODE_PWM;
|
|
} else if ((strcmp("auto", mode_name) == 0) &&
|
|
(vreg->regulator_type == QPNP_TYPE_FTS2
|
|
|| vreg->regulator_type == QPNP_TYPE_FTS2p5)) {
|
|
vreg->init_mode = QPNP_FTS2_MODE_AUTO;
|
|
} else {
|
|
dev_err(&vreg->spmi_dev->dev, "%s: unknown regulator mode: %s\n",
|
|
__func__, mode_name);
|
|
return -EINVAL;
|
|
}
|
|
|
|
rc = spmi_ext_register_writel(vreg->spmi_dev->ctrl,
|
|
vreg->spmi_dev->sid,
|
|
vreg->spmi_base_addr + QPNP_SMPS_REG_MODE,
|
|
&vreg->init_mode, 1);
|
|
if (rc)
|
|
dev_err(&vreg->spmi_dev->dev, "%s: could not write mode register, rc=%d\n",
|
|
__func__, rc);
|
|
} else {
|
|
rc = spmi_ext_register_readl(vreg->spmi_dev->ctrl,
|
|
vreg->spmi_dev->sid,
|
|
vreg->spmi_base_addr + QPNP_SMPS_REG_MODE,
|
|
&vreg->init_mode, 1);
|
|
if (rc)
|
|
dev_err(&vreg->spmi_dev->dev, "%s: could not read mode register, rc=%d\n",
|
|
__func__, rc);
|
|
}
|
|
|
|
vreg->mode = vreg->init_mode;
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int qpnp_smps_init_step_rate(struct spm_vreg *vreg)
|
|
{
|
|
int rc;
|
|
u8 reg = 0;
|
|
int step = 0, delay;
|
|
|
|
rc = spmi_ext_register_readl(vreg->spmi_dev->ctrl, vreg->spmi_dev->sid,
|
|
vreg->spmi_base_addr + QPNP_SMPS_REG_STEP_CTRL, ®, 1);
|
|
if (rc) {
|
|
dev_err(&vreg->spmi_dev->dev, "%s: could not read stepping control register, rc=%d\n",
|
|
__func__, rc);
|
|
return rc;
|
|
}
|
|
|
|
/* ULT buck does not support steps */
|
|
if (vreg->regulator_type != QPNP_TYPE_ULT_HF)
|
|
step = (reg & QPNP_FTS2_STEP_CTRL_STEP_MASK)
|
|
>> QPNP_FTS2_STEP_CTRL_STEP_SHIFT;
|
|
|
|
delay = (reg & QPNP_SMPS_STEP_CTRL_DELAY_MASK)
|
|
>> QPNP_SMPS_STEP_CTRL_DELAY_SHIFT;
|
|
|
|
/* step_rate has units of uV/us. */
|
|
vreg->step_rate = QPNP_FTS2_CLOCK_RATE * vreg->range->step_uV
|
|
* (1 << step);
|
|
|
|
if (vreg->regulator_type == QPNP_TYPE_ULT_HF)
|
|
vreg->step_rate /= 1000 * (QPNP_ULT_HF_STEP_DELAY << delay);
|
|
else
|
|
vreg->step_rate /= 1000 * (QPNP_FTS2_STEP_DELAY << delay);
|
|
|
|
vreg->step_rate = vreg->step_rate * QPNP_FTS2_STEP_MARGIN_NUM
|
|
/ QPNP_FTS2_STEP_MARGIN_DEN;
|
|
|
|
/* Ensure that the stepping rate is greater than 0. */
|
|
vreg->step_rate = max(vreg->step_rate, 1);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static bool spm_regulator_using_range0(struct spm_vreg *vreg)
|
|
{
|
|
return vreg->range == &fts2_range0 || vreg->range == &fts2p5_range0
|
|
|| vreg->range == &ult_hf_range0;
|
|
}
|
|
|
|
static int spm_regulator_probe(struct spmi_device *spmi)
|
|
{
|
|
struct regulator_config reg_config = {};
|
|
struct device_node *node = spmi->dev.of_node;
|
|
struct regulator_init_data *init_data;
|
|
struct spm_vreg *vreg;
|
|
struct resource *res;
|
|
bool bypass_spm;
|
|
int rc;
|
|
|
|
if (!node) {
|
|
dev_err(&spmi->dev, "%s: device node missing\n", __func__);
|
|
return -ENODEV;
|
|
}
|
|
|
|
bypass_spm = of_property_read_bool(node, "qcom,bypass-spm");
|
|
if (!bypass_spm) {
|
|
rc = msm_spm_probe_done();
|
|
if (rc) {
|
|
if (rc != -EPROBE_DEFER)
|
|
dev_err(&spmi->dev, "%s: spm unavailable, rc=%d\n",
|
|
__func__, rc);
|
|
return rc;
|
|
}
|
|
}
|
|
|
|
vreg = devm_kzalloc(&spmi->dev, sizeof(*vreg), GFP_KERNEL);
|
|
if (!vreg) {
|
|
pr_err("allocation failed.\n");
|
|
return -ENOMEM;
|
|
}
|
|
vreg->spmi_dev = spmi;
|
|
vreg->bypass_spm = bypass_spm;
|
|
|
|
res = spmi_get_resource(spmi, NULL, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
dev_err(&spmi->dev, "%s: node is missing base address\n",
|
|
__func__);
|
|
return -EINVAL;
|
|
}
|
|
vreg->spmi_base_addr = res->start;
|
|
|
|
rc = qpnp_smps_check_type(vreg);
|
|
if (rc)
|
|
return rc;
|
|
|
|
/* Specify CPU 0 as default in order to handle shared regulator case. */
|
|
vreg->cpu_num = 0;
|
|
of_property_read_u32(vreg->spmi_dev->dev.of_node, "qcom,cpu-num",
|
|
&vreg->cpu_num);
|
|
|
|
/*
|
|
* The regulator must be initialized to range 0 or range 1 during
|
|
* PMIC power on sequence. Once it is set, it cannot be changed
|
|
* dynamically.
|
|
*/
|
|
if (vreg->regulator_type == QPNP_TYPE_FTS2)
|
|
rc = qpnp_fts_init_range(vreg, &fts2_range0, &fts2_range1);
|
|
else if (vreg->regulator_type == QPNP_TYPE_FTS2p5)
|
|
rc = qpnp_fts_init_range(vreg, &fts2p5_range0, &fts2p5_range1);
|
|
else if (vreg->regulator_type == QPNP_TYPE_ULT_HF)
|
|
rc = qpnp_ult_hf_init_range(vreg);
|
|
if (rc)
|
|
return rc;
|
|
|
|
rc = qpnp_smps_init_voltage(vreg);
|
|
if (rc)
|
|
return rc;
|
|
|
|
rc = qpnp_smps_init_mode(vreg);
|
|
if (rc)
|
|
return rc;
|
|
|
|
rc = qpnp_smps_init_step_rate(vreg);
|
|
if (rc)
|
|
return rc;
|
|
|
|
init_data = of_get_regulator_init_data(&spmi->dev, node);
|
|
if (!init_data) {
|
|
dev_err(&spmi->dev, "%s: unable to allocate memory\n",
|
|
__func__);
|
|
return -ENOMEM;
|
|
}
|
|
init_data->constraints.input_uV = init_data->constraints.max_uV;
|
|
init_data->constraints.valid_ops_mask |= REGULATOR_CHANGE_STATUS
|
|
| REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE;
|
|
init_data->constraints.valid_modes_mask
|
|
= REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE;
|
|
|
|
if (!init_data->constraints.name) {
|
|
dev_err(&spmi->dev, "%s: node is missing regulator name\n",
|
|
__func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
vreg->rdesc.name = init_data->constraints.name;
|
|
vreg->rdesc.type = REGULATOR_VOLTAGE;
|
|
vreg->rdesc.owner = THIS_MODULE;
|
|
vreg->rdesc.ops = &spm_regulator_ops;
|
|
vreg->rdesc.n_voltages
|
|
= (vreg->range->max_uV - vreg->range->set_point_min_uV)
|
|
/ vreg->range->step_uV + 1;
|
|
|
|
reg_config.dev = &spmi->dev;
|
|
reg_config.init_data = init_data;
|
|
reg_config.driver_data = vreg;
|
|
reg_config.of_node = node;
|
|
vreg->rdev = regulator_register(&vreg->rdesc, ®_config);
|
|
if (IS_ERR(vreg->rdev)) {
|
|
rc = PTR_ERR(vreg->rdev);
|
|
dev_err(&spmi->dev, "%s: regulator_register failed, rc=%d\n",
|
|
__func__, rc);
|
|
return rc;
|
|
}
|
|
|
|
dev_set_drvdata(&spmi->dev, vreg);
|
|
|
|
pr_info("name=%s, range=%s, voltage=%d uV, mode=%s, step rate=%d uV/us\n",
|
|
vreg->rdesc.name,
|
|
spm_regulator_using_range0(vreg) ? "LV" : "MV",
|
|
vreg->uV,
|
|
vreg->init_mode & QPNP_SMPS_MODE_PWM ? "PWM" :
|
|
(vreg->init_mode & QPNP_FTS2_MODE_AUTO ? "AUTO" : "PFM"),
|
|
vreg->step_rate);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int spm_regulator_remove(struct spmi_device *spmi)
|
|
{
|
|
struct spm_vreg *vreg = dev_get_drvdata(&spmi->dev);
|
|
|
|
regulator_unregister(vreg->rdev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct of_device_id spm_regulator_match_table[] = {
|
|
{ .compatible = SPM_REGULATOR_DRIVER_NAME, },
|
|
{}
|
|
};
|
|
|
|
static const struct spmi_device_id spm_regulator_id[] = {
|
|
{ SPM_REGULATOR_DRIVER_NAME, 0 },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(spmi, spm_regulator_id);
|
|
|
|
static struct spmi_driver spm_regulator_driver = {
|
|
.driver = {
|
|
.name = SPM_REGULATOR_DRIVER_NAME,
|
|
.of_match_table = spm_regulator_match_table,
|
|
.owner = THIS_MODULE,
|
|
},
|
|
.probe = spm_regulator_probe,
|
|
.remove = spm_regulator_remove,
|
|
.id_table = spm_regulator_id,
|
|
};
|
|
|
|
/**
|
|
* spm_regulator_init() - register spmi driver for spm-regulator
|
|
*
|
|
* This initialization function should be called in systems in which driver
|
|
* registration ordering must be controlled precisely.
|
|
*
|
|
* Returns 0 on success or errno on failure.
|
|
*/
|
|
int __init spm_regulator_init(void)
|
|
{
|
|
static bool has_registered;
|
|
|
|
if (has_registered)
|
|
return 0;
|
|
else
|
|
has_registered = true;
|
|
|
|
return spmi_driver_register(&spm_regulator_driver);
|
|
}
|
|
EXPORT_SYMBOL(spm_regulator_init);
|
|
|
|
static void __exit spm_regulator_exit(void)
|
|
{
|
|
spmi_driver_unregister(&spm_regulator_driver);
|
|
}
|
|
|
|
arch_initcall(spm_regulator_init);
|
|
module_exit(spm_regulator_exit);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("SPM regulator driver");
|
|
MODULE_ALIAS("platform:spm-regulator");
|