642 lines
32 KiB
C
642 lines
32 KiB
C
/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef MSM8X10_WCD_REGISTERS_H
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#define MSM8X10_WCD_REGISTERS_H
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#define MSM8X10_WCD_A_CHIP_CTL (0x000)
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#define MSM8X10_WCD_A_CHIP_CTL__POR (0x04)
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#define MSM8X10_WCD_A_CHIP_STATUS (0x001)
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#define MSM8X10_WCD_A_CHIP_STATUS__POR (0x00)
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#define MSM8X10_WCD_A_CDC_TLMM_MODE_SELECT (0x002)
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#define MSM8X10_WCD_A_CDC_TLMM_MODE_SELECT__POR (0x00)
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#define MSM8X10_WCD_A_MODE_LOCK (0x003)
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#define MSM8X10_WCD_A_MODE_LOCK__POR (0x00)
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#define MSM8X10_WCD_A_CHIP_ID_BYTE_0 (0x004)
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#define MSM8X10_WCD_A_CHIP_ID_BYTE_0__POR (0x00)
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#define MSM8X10_WCD_A_CHIP_ID_BYTE_1 (0x005)
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#define MSM8X10_WCD_A_CHIP_ID_BYTE_1__POR (0x00)
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#define MSM8X10_WCD_A_CHIP_ID_BYTE_2 (0x006)
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#define MSM8X10_WCD_A_CHIP_ID_BYTE_2__POR (0x04)
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#define MSM8X10_WCD_A_CHIP_ID_BYTE_3 (0x007)
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#define MSM8X10_WCD_A_CHIP_ID_BYTE_3__POR (0x01)
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#define MSM8X10_WCD_A_CHIP_VERSION (0x008)
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#define MSM8X10_WCD_A_CHIP_VERSION__POR (0x00)
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#define MSM8X10_WCD_A_ANALOG_SLAVE_ID (0x00C)
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#define MSM8X10_WCD_A_ANALOG_SLAVE_ID__POR (0x77)
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#define MSM8X10_WCD_A_PIN_CTL_OE (0x010)
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#define MSM8X10_WCD_A_PIN_CTL_OE__POR (0x07)
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#define MSM8X10_WCD_A_PIN_CTL_DATA (0x012)
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#define MSM8X10_WCD_A_PIN_CTL_DATA__POR (0x00)
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#define MSM8X10_WCD_A_PIN_STATUS (0x014)
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#define MSM8X10_WCD_A_PIN_STATUS__POR (0x00)
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#define MSM8X10_WCD_A_HDRIVE_CTL (0x018)
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#define MSM8X10_WCD_A_HDRIVE_CTL__POR (0x01)
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#define MSM8X10_WCD_A_HDRIVE_I2C_CTL (0x019)
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#define MSM8X10_WCD_A_HDRIVE_I2C_CTL__POR (0x01)
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#define MSM8X10_WCD_A_CDC_RST_CTL (0x020)
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#define MSM8X10_WCD_A_CDC_RST_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_TOP_CLK_CTL (0x022)
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#define MSM8X10_WCD_A_CDC_TOP_CLK_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_ANA_CLK_CTL (0x023)
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#define MSM8X10_WCD_A_CDC_ANA_CLK_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_DIG_CLK_CTL (0x024)
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#define MSM8X10_WCD_A_CDC_DIG_CLK_CTL__POR (0x00)
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#define MSM8X10_WCD_A_PROCESS_MONITOR_CTL0 (0x030)
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#define MSM8X10_WCD_A_PROCESS_MONITOR_CTL0__POR (0x80)
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#define MSM8X10_WCD_A_PROCESS_MONITOR_CTL1 (0x031)
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#define MSM8X10_WCD_A_PROCESS_MONITOR_CTL1__POR (0x00)
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#define MSM8X10_WCD_A_PROCESS_MONITOR_CTL2 (0x032)
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#define MSM8X10_WCD_A_PROCESS_MONITOR_CTL2__POR (0x00)
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#define MSM8X10_WCD_A_PROCESS_MONITOR_CTL3 (0x033)
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#define MSM8X10_WCD_A_PROCESS_MONITOR_CTL3__POR (0x01)
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#define MSM8X10_WCD_A_QFUSE_CTL (0x034)
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#define MSM8X10_WCD_A_QFUSE_CTL__POR (0x00)
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#define MSM8X10_WCD_A_QFUSE_STATUS (0x035)
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#define MSM8X10_WCD_A_QFUSE_STATUS__POR (0x00)
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#define MSM8X10_WCD_A_QFUSE_DATA_OUT0 (0x036)
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#define MSM8X10_WCD_A_QFUSE_DATA_OUT0__POR (0x00)
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#define MSM8X10_WCD_A_QFUSE_DATA_OUT1 (0x037)
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#define MSM8X10_WCD_A_QFUSE_DATA_OUT1__POR (0x00)
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#define MSM8X10_WCD_A_QFUSE_DATA_OUT2 (0x038)
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#define MSM8X10_WCD_A_QFUSE_DATA_OUT2__POR (0x00)
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#define MSM8X10_WCD_A_QFUSE_DATA_OUT3 (0x039)
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#define MSM8X10_WCD_A_QFUSE_DATA_OUT3__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_TX1_CTL (0x040)
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#define MSM8X10_WCD_A_CDC_CONN_TX1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_TX2_CTL (0x041)
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#define MSM8X10_WCD_A_CDC_CONN_TX2_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_HPHR_DAC_CTL (0x042)
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#define MSM8X10_WCD_A_CDC_CONN_HPHR_DAC_CTL__POR (0x01)
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#define MSM8X10_WCD_A_CDC_CONN_LO_DAC_CTL (0x043)
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#define MSM8X10_WCD_A_CDC_CONN_LO_DAC_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_RX1_CTL (0x044)
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#define MSM8X10_WCD_A_CDC_CONN_RX1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_RX2_CTL (0x045)
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#define MSM8X10_WCD_A_CDC_CONN_RX2_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_RX3_CTL (0x046)
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#define MSM8X10_WCD_A_CDC_CONN_RX3_CTL__POR (0x00)
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#define MSM8X10_WCD_A_DIGITAL_DEBUG_CTL (0x048)
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#define MSM8X10_WCD_A_DIGITAL_DEBUG_CTL__POR (0x00)
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#define MSM8X10_WCD_A_ANALOG_DEBUG_CTL (0x049)
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#define MSM8X10_WCD_A_ANALOG_DEBUG_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_RX1_CTL (0x050)
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#define MSM8X10_WCD_A_CDC_RX1_CTL__POR (0x7C)
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#define MSM8X10_WCD_A_CDC_RX2_CTL (0x058)
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#define MSM8X10_WCD_A_CDC_RX2_CTL__POR (0x7C)
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#define MSM8X10_WCD_A_CDC_RX3_CTL (0x060)
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#define MSM8X10_WCD_A_CDC_RX3_CTL__POR (0x7C)
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#define MSM8X10_WCD_A_DEM_BYPASS_DATA0 (0x070)
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#define MSM8X10_WCD_A_DEM_BYPASS_DATA0__POR (0x00)
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#define MSM8X10_WCD_A_DEM_BYPASS_DATA1 (0x071)
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#define MSM8X10_WCD_A_DEM_BYPASS_DATA1__POR (0x00)
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#define MSM8X10_WCD_A_DEM_BYPASS_DATA2 (0x072)
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#define MSM8X10_WCD_A_DEM_BYPASS_DATA2__POR (0x00)
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#define MSM8X10_WCD_A_DEM_BYPASS_DATA3 (0x073)
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#define MSM8X10_WCD_A_DEM_BYPASS_DATA3__POR (0x00)
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#define MSM8X10_WCD_A_SPARE_0 (0x080)
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#define MSM8X10_WCD_A_SPARE_0__POR (0x00)
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#define MSM8X10_WCD_A_SPARE_1 (0x082)
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#define MSM8X10_WCD_A_SPARE_1__POR (0x00)
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#define MSM8X10_WCD_A_SPARE_2 (0x084)
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#define MSM8X10_WCD_A_SPARE_2__POR (0x00)
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#define MSM8X10_WCD_A_INTR_MODE (0x090)
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#define MSM8X10_WCD_A_INTR_MODE__POR (0x00)
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#define MSM8X10_WCD_A_INTR_MASK0 (0x094)
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#define MSM8X10_WCD_A_INTR_MASK0__POR (0xFF)
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#define MSM8X10_WCD_A_INTR_MASK1 (0x095)
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#define MSM8X10_WCD_A_INTR_MASK1__POR (0xFF)
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#define MSM8X10_WCD_A_INTR_MASK2 (0x096)
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#define MSM8X10_WCD_A_INTR_MASK2__POR (0x3F)
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#define MSM8X10_WCD_A_INTR_STATUS0 (0x098)
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#define MSM8X10_WCD_A_INTR_STATUS0__POR (0x00)
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#define MSM8X10_WCD_A_INTR_STATUS1 (0x099)
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#define MSM8X10_WCD_A_INTR_STATUS1__POR (0x00)
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#define MSM8X10_WCD_A_INTR_STATUS2 (0x09A)
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#define MSM8X10_WCD_A_INTR_STATUS2__POR (0x00)
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#define MSM8X10_WCD_A_INTR_CLEAR0 (0x09C)
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#define MSM8X10_WCD_A_INTR_CLEAR0__POR (0x00)
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#define MSM8X10_WCD_A_INTR_CLEAR1 (0x09D)
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#define MSM8X10_WCD_A_INTR_CLEAR1__POR (0x00)
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#define MSM8X10_WCD_A_INTR_CLEAR2 (0x09E)
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#define MSM8X10_WCD_A_INTR_CLEAR2__POR (0x00)
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#define MSM8X10_WCD_A_INTR_TEST0 (0x0A4)
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#define MSM8X10_WCD_A_INTR_TEST0__POR (0x00)
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#define MSM8X10_WCD_A_INTR_TEST1 (0x0A5)
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#define MSM8X10_WCD_A_INTR_TEST1__POR (0x00)
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#define MSM8X10_WCD_A_INTR_TEST2 (0x0A6)
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#define MSM8X10_WCD_A_INTR_TEST2__POR (0x00)
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#define MSM8X10_WCD_A_INTR_SET0 (0x0A8)
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#define MSM8X10_WCD_A_INTR_SET0__POR (0x00)
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#define MSM8X10_WCD_A_INTR_SET1 (0x0A9)
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#define MSM8X10_WCD_A_INTR_SET1__POR (0x00)
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#define MSM8X10_WCD_A_INTR_SET2 (0x0AA)
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#define MSM8X10_WCD_A_INTR_SET2__POR (0x00)
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#define MSM8X10_WCD_A_CDC_MBHC_EN_CTL (0x0C0)
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#define MSM8X10_WCD_A_CDC_MBHC_EN_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_MBHC_FIR_B1_CFG (0x0C1)
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#define MSM8X10_WCD_A_CDC_MBHC_FIR_B1_CFG__POR (0x00)
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#define MSM8X10_WCD_A_CDC_MBHC_FIR_B2_CFG (0x0C2)
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#define MSM8X10_WCD_A_CDC_MBHC_FIR_B2_CFG__POR (0x06)
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#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B1_CTL (0x0C3)
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#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B1_CTL__POR (0x03)
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#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B2_CTL (0x0C4)
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#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B2_CTL__POR (0x09)
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#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B3_CTL (0x0C5)
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#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B3_CTL__POR (0x1E)
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#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B4_CTL (0x0C6)
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#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B4_CTL__POR (0x45)
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#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B5_CTL (0x0C7)
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#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B5_CTL__POR (0x04)
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#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B6_CTL (0x0C8)
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#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B6_CTL__POR (0x78)
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#define MSM8X10_WCD_A_CDC_MBHC_B1_STATUS (0x0C9)
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#define MSM8X10_WCD_A_CDC_MBHC_B1_STATUS__POR (0x00)
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#define MSM8X10_WCD_A_CDC_MBHC_B2_STATUS (0x0CA)
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#define MSM8X10_WCD_A_CDC_MBHC_B2_STATUS__POR (0x00)
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#define MSM8X10_WCD_A_CDC_MBHC_B3_STATUS (0x0CB)
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#define MSM8X10_WCD_A_CDC_MBHC_B3_STATUS__POR (0x00)
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#define MSM8X10_WCD_A_CDC_MBHC_B4_STATUS (0x0CC)
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#define MSM8X10_WCD_A_CDC_MBHC_B4_STATUS__POR (0x00)
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#define MSM8X10_WCD_A_CDC_MBHC_B5_STATUS (0x0CD)
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#define MSM8X10_WCD_A_CDC_MBHC_B5_STATUS__POR (0x00)
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#define MSM8X10_WCD_A_CDC_MBHC_B1_CTL (0x0CE)
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#define MSM8X10_WCD_A_CDC_MBHC_B1_CTL__POR (0xC0)
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#define MSM8X10_WCD_A_CDC_MBHC_B2_CTL (0x0CF)
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#define MSM8X10_WCD_A_CDC_MBHC_B2_CTL__POR (0x5D)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B1_CTL (0x0D0)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B2_CTL (0x0D1)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B3_CTL (0x0D2)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B4_CTL (0x0D3)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B5_CTL (0x0D4)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B6_CTL (0x0D5)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B7_CTL (0x0D6)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B7_CTL__POR (0xFF)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B8_CTL (0x0D7)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B8_CTL__POR (0x07)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B9_CTL (0x0D8)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B9_CTL__POR (0xFF)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B10_CTL (0x0D9)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B10_CTL__POR (0x7F)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B11_CTL (0x0DA)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B12_CTL (0x0DB)
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#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B12_CTL__POR (0x80)
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#define MSM8X10_WCD_A_CDC_MBHC_CLK_CTL (0x0DC)
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#define MSM8X10_WCD_A_CDC_MBHC_CLK_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_MBHC_INT_CTL (0x0DD)
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#define MSM8X10_WCD_A_CDC_MBHC_INT_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_MBHC_DEBUG_CTL (0x0DE)
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#define MSM8X10_WCD_A_CDC_MBHC_DEBUG_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_MBHC_SPARE (0x0DF)
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#define MSM8X10_WCD_A_CDC_MBHC_SPARE__POR (0x00)
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#define MSM8X10_WCD_A_BIAS_REF_CTL (0x100)
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#define MSM8X10_WCD_A_BIAS_REF_CTL__POR (0x1C)
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#define MSM8X10_WCD_A_BIAS_CENTRAL_BG_CTL (0x101)
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#define MSM8X10_WCD_A_BIAS_CENTRAL_BG_CTL__POR (0x50)
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#define MSM8X10_WCD_A_BIAS_PRECHRG_CTL (0x102)
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#define MSM8X10_WCD_A_BIAS_PRECHRG_CTL__POR (0x07)
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#define MSM8X10_WCD_A_BIAS_CURR_CTL_1 (0x103)
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#define MSM8X10_WCD_A_BIAS_CURR_CTL_1__POR (0x52)
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#define MSM8X10_WCD_A_BIAS_CURR_CTL_2 (0x104)
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#define MSM8X10_WCD_A_BIAS_CURR_CTL_2__POR (0x00)
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#define MSM8X10_WCD_A_BIAS_OSC_BG_CTL (0x105)
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#define MSM8X10_WCD_A_BIAS_OSC_BG_CTL__POR (0x16)
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#define MSM8X10_WCD_A_MICB_CFILT_1_CTL (0x128)
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#define MSM8X10_WCD_A_MICB_CFILT_1_CTL__POR (0x40)
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#define MSM8X10_WCD_A_MICB_CFILT_1_VAL (0x129)
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#define MSM8X10_WCD_A_MICB_CFILT_1_VAL__POR (0x80)
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#define MSM8X10_WCD_A_MICB_CFILT_1_PRECHRG (0x12A)
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#define MSM8X10_WCD_A_MICB_CFILT_1_PRECHRG__POR (0x00)
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#define MSM8X10_WCD_A_MICB_1_CTL (0x12B)
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#define MSM8X10_WCD_A_MICB_1_CTL__POR (0x02)
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#define MSM8X10_WCD_A_MICB_1_INT_RBIAS (0x12C)
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#define MSM8X10_WCD_A_MICB_1_INT_RBIAS__POR (0x00)
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#define MSM8X10_WCD_A_MICB_1_MBHC (0x12D)
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#define MSM8X10_WCD_A_MICB_1_MBHC__POR (0x00)
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#define MSM8X10_WCD_A_MBHC_INSERT_DETECT (0x14A)
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#define MSM8X10_WCD_A_MBHC_INSERT_DETECT__POR (0x00)
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#define MSM8X10_WCD_A_MBHC_INSERT_DET_STATUS (0x14B)
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#define MSM8X10_WCD_A_MBHC_INSERT_DET_STATUS__POR (0x00)
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#define MSM8X10_WCD_A_TX_COM_BIAS (0x14C)
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#define MSM8X10_WCD_A_TX_COM_BIAS__POR (0xF0)
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#define MSM8X10_WCD_A_MBHC_SCALING_MUX_1 (0x14E)
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#define MSM8X10_WCD_A_MBHC_SCALING_MUX_1__POR (0x00)
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#define MSM8X10_WCD_A_MBHC_SCALING_MUX_2 (0x14F)
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#define MSM8X10_WCD_A_MBHC_SCALING_MUX_2__POR (0x80)
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#define MSM8X10_WCD_A_RESERVED_MAD_ANA_CTRL (0x150)
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#define MSM8X10_WCD_A_RESERVED_MAD_ANA_CTRL__POR (0xF1)
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#define MSM8X10_WCD_A_TX_SUP_SWITCH_CTRL_1 (0x151)
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#define MSM8X10_WCD_A_TX_SUP_SWITCH_CTRL_1__POR (0x00)
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#define MSM8X10_WCD_A_TX_SUP_SWITCH_CTRL_2 (0x152)
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#define MSM8X10_WCD_A_TX_SUP_SWITCH_CTRL_2__POR (0x80)
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#define MSM8X10_WCD_A_TX_1_EN (0x153)
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#define MSM8X10_WCD_A_TX_1_EN__POR (0x02)
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#define MSM8X10_WCD_A_TX_2_EN (0x154)
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#define MSM8X10_WCD_A_TX_2_EN__POR (0x02)
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#define MSM8X10_WCD_A_TX_1_2_ADC_CH1 (0x155)
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#define MSM8X10_WCD_A_TX_1_2_ADC_CH1__POR (0x44)
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#define MSM8X10_WCD_A_TX_1_2_ADC_CH2 (0x156)
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#define MSM8X10_WCD_A_TX_1_2_ADC_CH2__POR (0x44)
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#define MSM8X10_WCD_A_TX_1_2_ATEST_REFCTRL (0x157)
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#define MSM8X10_WCD_A_TX_1_2_ATEST_REFCTRL__POR (0x00)
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#define MSM8X10_WCD_A_TX_1_2_TEST_CTL (0x158)
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#define MSM8X10_WCD_A_TX_1_2_TEST_CTL__POR (0x38)
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#define MSM8X10_WCD_A_TX_1_2_TEST_BLOCK_EN (0x159)
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#define MSM8X10_WCD_A_TX_1_2_TEST_BLOCK_EN__POR (0xFC)
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#define MSM8X10_WCD_A_TX_1_2_TXFE_CLKDIV (0x15A)
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#define MSM8X10_WCD_A_TX_1_2_TXFE_CLKDIV__POR (0x55)
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#define MSM8X10_WCD_A_TX_1_2_SAR_ERR_CH1 (0x15B)
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#define MSM8X10_WCD_A_TX_1_2_SAR_ERR_CH1__POR (0x00)
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#define MSM8X10_WCD_A_TX_1_2_SAR_ERR_CH2 (0x15C)
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#define MSM8X10_WCD_A_TX_1_2_SAR_ERR_CH2__POR (0x00)
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#define MSM8X10_WCD_A_TX_3_EN (0x15D)
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#define MSM8X10_WCD_A_TX_3_EN__POR (0x00)
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#define MSM8X10_WCD_A_TX_1_2_TEST_EN (0x15E)
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#define MSM8X10_WCD_A_TX_1_2_TEST_EN__POR (0xCC)
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#define MSM8X10_WCD_A_TX_7_MBHC_EN_ATEST_CTRL (0x171)
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#define MSM8X10_WCD_A_TX_7_MBHC_EN_ATEST_CTRL__POR (0x10)
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#define MSM8X10_WCD_A_TX_7_MBHC_SAR_ERR (0x175)
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#define MSM8X10_WCD_A_TX_7_MBHC_SAR_ERR__POR (0x00)
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#define MSM8X10_WCD_A_CP_EN (0x192)
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#define MSM8X10_WCD_A_CP_EN__POR (0xE6)
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#define MSM8X10_WCD_A_CP_CLK (0x193)
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#define MSM8X10_WCD_A_CP_CLK__POR (0x29)
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#define MSM8X10_WCD_A_CP_STATIC (0x194)
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#define MSM8X10_WCD_A_CP_STATIC__POR (0x10)
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#define MSM8X10_WCD_A_CP_DCC1 (0x195)
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#define MSM8X10_WCD_A_CP_DCC1__POR (0x52)
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#define MSM8X10_WCD_A_CP_DCC3 (0x196)
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#define MSM8X10_WCD_A_CP_DCC3__POR (0x01)
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#define MSM8X10_WCD_A_CP_ATEST (0x197)
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#define MSM8X10_WCD_A_CP_ATEST__POR (0x00)
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#define MSM8X10_WCD_A_CP_DTEST (0x198)
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#define MSM8X10_WCD_A_CP_DTEST__POR (0x00)
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#define MSM8X10_WCD_A_RX_AUX_SW_CTL (0x19B)
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#define MSM8X10_WCD_A_RX_AUX_SW_CTL__POR (0x00)
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#define MSM8X10_WCD_A_RX_PA_AUX_IN_CONN (0x19C)
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#define MSM8X10_WCD_A_RX_PA_AUX_IN_CONN__POR (0x00)
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#define MSM8X10_WCD_A_RX_COM_TIMER_DIV (0x19E)
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#define MSM8X10_WCD_A_RX_COM_TIMER_DIV__POR (0xE8)
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#define MSM8X10_WCD_A_RX_COM_OCP_CTL (0x19F)
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#define MSM8X10_WCD_A_RX_COM_OCP_CTL__POR (0x1F)
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#define MSM8X10_WCD_A_RX_COM_OCP_COUNT (0x1A0)
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#define MSM8X10_WCD_A_RX_COM_OCP_COUNT__POR (0x77)
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#define MSM8X10_WCD_A_RX_COM_DAC_CTL (0x1A1)
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#define MSM8X10_WCD_A_RX_COM_DAC_CTL__POR (0x00)
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#define MSM8X10_WCD_A_RX_COM_BIAS (0x1A2)
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#define MSM8X10_WCD_A_RX_COM_BIAS__POR (0x00)
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#define MSM8X10_WCD_A_RX_HPH_AUTO_CHOP (0x1A4)
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#define MSM8X10_WCD_A_RX_HPH_AUTO_CHOP__POR (0x38)
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#define MSM8X10_WCD_A_RX_HPH_CHOP_CTL (0x1A5)
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#define MSM8X10_WCD_A_RX_HPH_CHOP_CTL__POR (0x34)
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#define MSM8X10_WCD_A_RX_HPH_BIAS_PA (0x1A6)
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#define MSM8X10_WCD_A_RX_HPH_BIAS_PA__POR (0x5A)
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#define MSM8X10_WCD_A_RX_HPH_BIAS_LDO (0x1A7)
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#define MSM8X10_WCD_A_RX_HPH_BIAS_LDO__POR (0x87)
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#define MSM8X10_WCD_A_RX_HPH_BIAS_CNP (0x1A8)
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#define MSM8X10_WCD_A_RX_HPH_BIAS_CNP__POR (0x8A)
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#define MSM8X10_WCD_A_RX_HPH_BIAS_WG_OCP (0x1A9)
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#define MSM8X10_WCD_A_RX_HPH_BIAS_WG_OCP__POR (0x2A)
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#define MSM8X10_WCD_A_RX_HPH_OCP_CTL (0x1AA)
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#define MSM8X10_WCD_A_RX_HPH_OCP_CTL__POR (0x69)
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#define MSM8X10_WCD_A_RX_HPH_CNP_EN (0x1AB)
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#define MSM8X10_WCD_A_RX_HPH_CNP_EN__POR (0x80)
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#define MSM8X10_WCD_A_RX_HPH_CNP_WG_CTL (0x1AC)
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#define MSM8X10_WCD_A_RX_HPH_CNP_WG_CTL__POR (0xDE)
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#define MSM8X10_WCD_A_RX_HPH_CNP_WG_TIME (0x1AD)
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#define MSM8X10_WCD_A_RX_HPH_CNP_WG_TIME__POR (0x15)
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#define MSM8X10_WCD_A_RX_HPH_L_GAIN (0x1AE)
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#define MSM8X10_WCD_A_RX_HPH_L_GAIN__POR (0x00)
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#define MSM8X10_WCD_A_RX_HPH_L_TEST (0x1AF)
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#define MSM8X10_WCD_A_RX_HPH_L_TEST__POR (0x00)
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#define MSM8X10_WCD_A_RX_HPH_L_PA_CTL (0x1B0)
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#define MSM8X10_WCD_A_RX_HPH_L_PA_CTL__POR (0x40)
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#define MSM8X10_WCD_A_RX_HPH_L_DAC_CTL (0x1B1)
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#define MSM8X10_WCD_A_RX_HPH_L_DAC_CTL__POR (0x00)
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#define MSM8X10_WCD_A_RX_HPH_L_ATEST (0x1B2)
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#define MSM8X10_WCD_A_RX_HPH_L_ATEST__POR (0x00)
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#define MSM8X10_WCD_A_RX_HPH_L_STATUS (0x1B3)
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#define MSM8X10_WCD_A_RX_HPH_L_STATUS__POR (0x00)
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#define MSM8X10_WCD_A_RX_HPH_R_GAIN (0x1B4)
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#define MSM8X10_WCD_A_RX_HPH_R_GAIN__POR (0x00)
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#define MSM8X10_WCD_A_RX_HPH_R_TEST (0x1B5)
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#define MSM8X10_WCD_A_RX_HPH_R_TEST__POR (0x00)
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#define MSM8X10_WCD_A_RX_HPH_R_PA_CTL (0x1B6)
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#define MSM8X10_WCD_A_RX_HPH_R_PA_CTL__POR (0x40)
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#define MSM8X10_WCD_A_RX_HPH_R_DAC_CTL (0x1B7)
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#define MSM8X10_WCD_A_RX_HPH_R_DAC_CTL__POR (0x00)
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#define MSM8X10_WCD_A_RX_HPH_R_ATEST (0x1B8)
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#define MSM8X10_WCD_A_RX_HPH_R_ATEST__POR (0x00)
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#define MSM8X10_WCD_A_RX_HPH_R_STATUS (0x1B9)
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#define MSM8X10_WCD_A_RX_HPH_R_STATUS__POR (0x00)
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#define MSM8X10_WCD_A_RX_EAR_BIAS_PA (0x1BA)
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#define MSM8X10_WCD_A_RX_EAR_BIAS_PA__POR (0x56)
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#define MSM8X10_WCD_A_RX_EAR_BIAS_CMBUFF (0x1BB)
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#define MSM8X10_WCD_A_RX_EAR_BIAS_CMBUFF__POR (0xA0)
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#define MSM8X10_WCD_A_RX_EAR_EN (0x1BC)
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#define MSM8X10_WCD_A_RX_EAR_EN__POR (0x00)
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#define MSM8X10_WCD_A_RX_EAR_GAIN (0x1BD)
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#define MSM8X10_WCD_A_RX_EAR_GAIN__POR (0x02)
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#define MSM8X10_WCD_A_RX_EAR_CMBUFF (0x1BE)
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#define MSM8X10_WCD_A_RX_EAR_CMBUFF__POR (0x05)
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#define MSM8X10_WCD_A_RX_EAR_ICTL (0x1BF)
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#define MSM8X10_WCD_A_RX_EAR_ICTL__POR (0x40)
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#define MSM8X10_WCD_A_RX_EAR_CCOMP (0x1C0)
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#define MSM8X10_WCD_A_RX_EAR_CCOMP__POR (0x08)
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#define MSM8X10_WCD_A_RX_EAR_VCM (0x1C1)
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#define MSM8X10_WCD_A_RX_EAR_VCM__POR (0x03)
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#define MSM8X10_WCD_A_RX_EAR_CNP (0x1C2)
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#define MSM8X10_WCD_A_RX_EAR_CNP__POR (0xF2)
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#define MSM8X10_WCD_A_RX_EAR_DAC_CTL_ATEST (0x1C3)
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#define MSM8X10_WCD_A_RX_EAR_DAC_CTL_ATEST__POR (0x00)
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#define MSM8X10_WCD_A_RX_EAR_STATUS (0x1C5)
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#define MSM8X10_WCD_A_RX_EAR_STATUS__POR (0x04)
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#define MSM8X10_WCD_A_RX_LINE_BIAS_PA (0x1C6)
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#define MSM8X10_WCD_A_RX_LINE_BIAS_PA__POR (0x58)
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#define MSM8X10_WCD_A_RX_BUCK_BIAS1 (0x1C7)
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#define MSM8X10_WCD_A_RX_BUCK_BIAS1__POR (0x42)
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#define MSM8X10_WCD_A_RX_BUCK_BIAS2 (0x1C8)
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#define MSM8X10_WCD_A_RX_BUCK_BIAS2__POR (0x84)
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#define MSM8X10_WCD_A_RX_LINE_COM (0x1C9)
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#define MSM8X10_WCD_A_RX_LINE_COM__POR (0x80)
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#define MSM8X10_WCD_A_RX_LINE_CNP_EN (0x1CA)
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#define MSM8X10_WCD_A_RX_LINE_CNP_EN__POR (0x00)
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#define MSM8X10_WCD_A_RX_LINE_CNP_WG_CTL (0x1CB)
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#define MSM8X10_WCD_A_RX_LINE_CNP_WG_CTL__POR (0x00)
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#define MSM8X10_WCD_A_RX_LINE_CNP_WG_TIME (0x1CC)
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#define MSM8X10_WCD_A_RX_LINE_CNP_WG_TIME__POR (0x04)
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#define MSM8X10_WCD_A_RX_LINE_1_GAIN (0x1CD)
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#define MSM8X10_WCD_A_RX_LINE_1_GAIN__POR (0x00)
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#define MSM8X10_WCD_A_RX_LINE_1_TEST (0x1CE)
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#define MSM8X10_WCD_A_RX_LINE_1_TEST__POR (0x00)
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#define MSM8X10_WCD_A_RX_LINE_1_DAC_CTL (0x1CF)
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#define MSM8X10_WCD_A_RX_LINE_1_DAC_CTL__POR (0x00)
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#define MSM8X10_WCD_A_RX_LINE_1_STATUS (0x1D0)
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#define MSM8X10_WCD_A_RX_LINE_1_STATUS__POR (0x00)
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#define MSM8X10_WCD_A_RX_LINE_CNP_DBG (0x1DD)
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#define MSM8X10_WCD_A_RX_LINE_CNP_DBG__POR (0x00)
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#define MSM8X10_WCD_A_SPKR_DRV_EN (0x1DF)
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#define MSM8X10_WCD_A_SPKR_DRV_EN__POR (0x6F)
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#define MSM8X10_WCD_A_SPKR_DRV_GAIN (0x1E0)
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#define MSM8X10_WCD_A_SPKR_DRV_GAIN__POR (0x00)
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#define MSM8X10_WCD_A_SPKR_DRV_DAC_CTL (0x1E1)
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#define MSM8X10_WCD_A_SPKR_DRV_DAC_CTL__POR (0x04)
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#define MSM8X10_WCD_A_SPKR_DRV_OCP_CTL (0x1E2)
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#define MSM8X10_WCD_A_SPKR_DRV_OCP_CTL__POR (0x98)
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#define MSM8X10_WCD_A_SPKR_DRV_CLIP_DET (0x1E3)
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#define MSM8X10_WCD_A_SPKR_DRV_CLIP_DET__POR (0x01)
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#define MSM8X10_WCD_A_SPKR_DRV_IEC (0x1E4)
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#define MSM8X10_WCD_A_SPKR_DRV_IEC__POR (0x00)
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#define MSM8X10_WCD_A_SPKR_DRV_DBG_DAC (0x1E5)
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#define MSM8X10_WCD_A_SPKR_DRV_DBG_DAC__POR (0x05)
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#define MSM8X10_WCD_A_SPKR_DRV_DBG_PA (0x1E6)
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#define MSM8X10_WCD_A_SPKR_DRV_DBG_PA__POR (0x18)
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#define MSM8X10_WCD_A_SPKR_DRV_DBG_PWRSTG (0x1E7)
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#define MSM8X10_WCD_A_SPKR_DRV_DBG_PWRSTG__POR (0x00)
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#define MSM8X10_WCD_A_SPKR_DRV_BIAS_LDO (0x1E8)
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#define MSM8X10_WCD_A_SPKR_DRV_BIAS_LDO__POR (0x45)
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#define MSM8X10_WCD_A_SPKR_DRV_BIAS_INT (0x1E9)
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#define MSM8X10_WCD_A_SPKR_DRV_BIAS_INT__POR (0xA5)
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#define MSM8X10_WCD_A_SPKR_DRV_BIAS_PA (0x1EA)
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#define MSM8X10_WCD_A_SPKR_DRV_BIAS_PA__POR (0x55)
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#define MSM8X10_WCD_A_SPKR_DRV_STATUS_OCP (0x1EB)
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#define MSM8X10_WCD_A_SPKR_DRV_STATUS_OCP__POR (0x00)
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#define MSM8X10_WCD_A_SPKR_DRV_STATUS_PA (0x1EC)
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#define MSM8X10_WCD_A_SPKR_DRV_STATUS_PA__POR (0x00)
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#define MSM8X10_WCD_A_RC_OSC_FREQ (0x1FA)
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#define MSM8X10_WCD_A_RC_OSC_FREQ__POR (0x46)
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#define MSM8X10_WCD_A_RC_OSC_TEST (0x1FB)
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#define MSM8X10_WCD_A_RC_OSC_TEST__POR (0x0A)
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#define MSM8X10_WCD_A_RC_OSC_STATUS (0x1FC)
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#define MSM8X10_WCD_A_RC_OSC_STATUS__POR (0x18)
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#define MSM8X10_WCD_A_RC_OSC_TUNER (0x1FD)
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#define MSM8X10_WCD_A_RC_OSC_TUNER__POR (0x00)
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#define MSM8X10_WCD_A_MBHC_HPH (0x1FE)
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#define MSM8X10_WCD_A_MBHC_HPH__POR (0x44)
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#define MSM8X10_WCD_A_CDC_CLK_RX_RESET_CTL (0x400)
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#define MSM8X10_WCD_A_CDC_CLK_RX_RESET_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CLK_TX_RESET_B1_CTL (0x404)
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#define MSM8X10_WCD_A_CDC_CLK_TX_RESET_B1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CLK_DMIC_B1_CTL (0x408)
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#define MSM8X10_WCD_A_CDC_CLK_DMIC_B1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CLK_RX_I2S_CTL (0x40C)
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#define MSM8X10_WCD_A_CDC_CLK_RX_I2S_CTL__POR (0x10)
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#define MSM8X10_WCD_A_CDC_CLK_TX_I2S_CTL (0x410)
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#define MSM8X10_WCD_A_CDC_CLK_TX_I2S_CTL__POR (0x10)
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#define MSM8X10_WCD_A_CDC_CLK_OTHR_RESET_B1_CTL (0x414)
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#define MSM8X10_WCD_A_CDC_CLK_OTHR_RESET_B1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL (0x418)
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#define MSM8X10_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CLK_OTHR_CTL (0x41C)
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#define MSM8X10_WCD_A_CDC_CLK_OTHR_CTL__POR (0x04)
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#define MSM8X10_WCD_A_CDC_CLK_RX_B1_CTL (0x420)
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#define MSM8X10_WCD_A_CDC_CLK_RX_B1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CLK_MCLK_CTL (0x424)
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#define MSM8X10_WCD_A_CDC_CLK_MCLK_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CLK_PDM_CTL (0x428)
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#define MSM8X10_WCD_A_CDC_CLK_PDM_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CLK_SD_CTL (0x42C)
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#define MSM8X10_WCD_A_CDC_CLK_SD_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_RX1_B1_CTL (0x440)
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#define MSM8X10_WCD_A_CDC_RX1_B1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_RX2_B1_CTL (0x460)
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#define MSM8X10_WCD_A_CDC_RX2_B1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_RX3_B1_CTL (0x480)
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#define MSM8X10_WCD_A_CDC_RX3_B1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_RX1_B2_CTL (0x444)
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#define MSM8X10_WCD_A_CDC_RX1_B2_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_RX2_B2_CTL (0x464)
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#define MSM8X10_WCD_A_CDC_RX2_B2_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_RX3_B2_CTL (0x484)
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#define MSM8X10_WCD_A_CDC_RX3_B2_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_RX1_B3_CTL (0x448)
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#define MSM8X10_WCD_A_CDC_RX1_B3_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_RX2_B3_CTL (0x468)
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#define MSM8X10_WCD_A_CDC_RX2_B3_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_RX3_B3_CTL (0x488)
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#define MSM8X10_WCD_A_CDC_RX3_B3_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_RX1_B4_CTL (0x44C)
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#define MSM8X10_WCD_A_CDC_RX1_B4_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_RX2_B4_CTL (0x46C)
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#define MSM8X10_WCD_A_CDC_RX2_B4_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_RX3_B4_CTL (0x48C)
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#define MSM8X10_WCD_A_CDC_RX3_B4_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_RX1_B5_CTL (0x450)
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#define MSM8X10_WCD_A_CDC_RX1_B5_CTL__POR (0x68)
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#define MSM8X10_WCD_A_CDC_RX2_B5_CTL (0x470)
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#define MSM8X10_WCD_A_CDC_RX2_B5_CTL__POR (0x68)
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#define MSM8X10_WCD_A_CDC_RX3_B5_CTL (0x490)
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#define MSM8X10_WCD_A_CDC_RX3_B5_CTL__POR (0x68)
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#define MSM8X10_WCD_A_CDC_RX1_B6_CTL (0x454)
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#define MSM8X10_WCD_A_CDC_RX1_B6_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_RX2_B6_CTL (0x474)
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#define MSM8X10_WCD_A_CDC_RX2_B6_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_RX3_B6_CTL (0x494)
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#define MSM8X10_WCD_A_CDC_RX3_B6_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_RX1_VOL_CTL_B1_CTL (0x458)
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#define MSM8X10_WCD_A_CDC_RX1_VOL_CTL_B1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_RX2_VOL_CTL_B1_CTL (0x478)
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#define MSM8X10_WCD_A_CDC_RX2_VOL_CTL_B1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_RX3_VOL_CTL_B1_CTL (0x498)
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#define MSM8X10_WCD_A_CDC_RX3_VOL_CTL_B1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_RX1_VOL_CTL_B2_CTL (0x45C)
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#define MSM8X10_WCD_A_CDC_RX1_VOL_CTL_B2_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_RX2_VOL_CTL_B2_CTL (0x47C)
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#define MSM8X10_WCD_A_CDC_RX2_VOL_CTL_B2_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_RX3_VOL_CTL_B2_CTL (0x49C)
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#define MSM8X10_WCD_A_CDC_RX3_VOL_CTL_B2_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B1_CTL (0x4A0)
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#define MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B1_CTL__POR (0x07)
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#define MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B2_CTL (0x4A4)
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#define MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B2_CTL__POR (0x13)
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#define MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B3_CTL (0x4A8)
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#define MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B3_CTL__POR (0x1B)
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#define MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B4_CTL (0x4AC)
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#define MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B4_CTL__POR (0x7F)
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#define MSM8X10_WCD_A_CDC_CLSG_GAIN_THRESH_CTL (0x4B0)
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#define MSM8X10_WCD_A_CDC_CLSG_GAIN_THRESH_CTL__POR (0x26)
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#define MSM8X10_WCD_A_CDC_CLSG_TIMER_B1_CFG (0x4B4)
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#define MSM8X10_WCD_A_CDC_CLSG_TIMER_B1_CFG__POR (0x0A)
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#define MSM8X10_WCD_A_CDC_CLSG_TIMER_B2_CFG (0x4B8)
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#define MSM8X10_WCD_A_CDC_CLSG_TIMER_B2_CFG__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CLSG_CTL (0x4BC)
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#define MSM8X10_WCD_A_CDC_CLSG_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_TX1_VOL_CTL_TIMER (0x4C0)
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#define MSM8X10_WCD_A_CDC_TX1_VOL_CTL_TIMER__POR (0x00)
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#define MSM8X10_WCD_A_CDC_TX2_VOL_CTL_TIMER (0x4E0)
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#define MSM8X10_WCD_A_CDC_TX2_VOL_CTL_TIMER__POR (0x00)
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#define MSM8X10_WCD_A_CDC_TX1_VOL_CTL_GAIN (0x4C4)
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#define MSM8X10_WCD_A_CDC_TX1_VOL_CTL_GAIN__POR (0x00)
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#define MSM8X10_WCD_A_CDC_TX2_VOL_CTL_GAIN (0x4E4)
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#define MSM8X10_WCD_A_CDC_TX2_VOL_CTL_GAIN__POR (0x00)
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#define MSM8X10_WCD_A_CDC_TX1_VOL_CTL_CFG (0x4C8)
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#define MSM8X10_WCD_A_CDC_TX1_VOL_CTL_CFG__POR (0x00)
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#define MSM8X10_WCD_A_CDC_TX2_VOL_CTL_CFG (0x4E8)
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#define MSM8X10_WCD_A_CDC_TX2_VOL_CTL_CFG__POR (0x00)
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#define MSM8X10_WCD_A_CDC_TX1_MUX_CTL (0x4CC)
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#define MSM8X10_WCD_A_CDC_TX1_MUX_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_TX2_MUX_CTL (0x4EC)
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#define MSM8X10_WCD_A_CDC_TX2_MUX_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_TX1_CLK_FS_CTL (0x4D0)
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#define MSM8X10_WCD_A_CDC_TX1_CLK_FS_CTL__POR (0x03)
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#define MSM8X10_WCD_A_CDC_TX2_CLK_FS_CTL (0x4F0)
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#define MSM8X10_WCD_A_CDC_TX2_CLK_FS_CTL__POR (0x03)
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#define MSM8X10_WCD_A_CDC_TX1_DMIC_CTL (0x4D4)
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#define MSM8X10_WCD_A_CDC_TX1_DMIC_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_TX2_DMIC_CTL (0x4F4)
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#define MSM8X10_WCD_A_CDC_TX2_DMIC_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B1_CTL (0x500)
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#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B1_CTL (0x540)
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#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B2_CTL (0x504)
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#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B2_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B2_CTL (0x544)
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#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B2_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B3_CTL (0x508)
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#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B3_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B3_CTL (0x548)
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#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B3_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B4_CTL (0x50C)
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#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B4_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B4_CTL (0x54C)
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#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B4_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B5_CTL (0x510)
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#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B5_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B5_CTL (0x550)
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#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B5_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B6_CTL (0x514)
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#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B6_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B6_CTL (0x554)
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#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B6_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B7_CTL (0x518)
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#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B7_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B7_CTL (0x558)
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#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B7_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B8_CTL (0x51C)
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#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B8_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B8_CTL (0x55C)
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#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B8_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_IIR1_CTL (0x520)
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#define MSM8X10_WCD_A_CDC_IIR1_CTL__POR (0x40)
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#define MSM8X10_WCD_A_CDC_IIR2_CTL (0x560)
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#define MSM8X10_WCD_A_CDC_IIR2_CTL__POR (0x40)
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#define MSM8X10_WCD_A_CDC_IIR1_GAIN_TIMER_CTL (0x524)
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#define MSM8X10_WCD_A_CDC_IIR1_GAIN_TIMER_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_IIR2_GAIN_TIMER_CTL (0x564)
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#define MSM8X10_WCD_A_CDC_IIR2_GAIN_TIMER_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_IIR1_COEF_B1_CTL (0x528)
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#define MSM8X10_WCD_A_CDC_IIR1_COEF_B1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_IIR2_COEF_B1_CTL (0x568)
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#define MSM8X10_WCD_A_CDC_IIR2_COEF_B1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_IIR1_COEF_B2_CTL (0x52C)
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#define MSM8X10_WCD_A_CDC_IIR1_COEF_B2_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_IIR2_COEF_B2_CTL (0x56C)
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#define MSM8X10_WCD_A_CDC_IIR2_COEF_B2_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_RX1_B1_CTL (0x580)
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#define MSM8X10_WCD_A_CDC_CONN_RX1_B1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_RX1_B2_CTL (0x584)
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#define MSM8X10_WCD_A_CDC_CONN_RX1_B2_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_RX1_B3_CTL (0x588)
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#define MSM8X10_WCD_A_CDC_CONN_RX1_B3_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_RX2_B1_CTL (0x58C)
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#define MSM8X10_WCD_A_CDC_CONN_RX2_B1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_RX2_B2_CTL (0x590)
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#define MSM8X10_WCD_A_CDC_CONN_RX2_B2_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_RX2_B3_CTL (0x594)
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#define MSM8X10_WCD_A_CDC_CONN_RX2_B3_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_RX3_B1_CTL (0x598)
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#define MSM8X10_WCD_A_CDC_CONN_RX3_B1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_RX3_B2_CTL (0x59C)
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#define MSM8X10_WCD_A_CDC_CONN_RX3_B2_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_TX_B1_CTL (0x5A4)
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#define MSM8X10_WCD_A_CDC_CONN_TX_B1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_EQ1_B1_CTL (0x5A8)
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#define MSM8X10_WCD_A_CDC_CONN_EQ1_B1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_EQ1_B2_CTL (0x5AC)
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#define MSM8X10_WCD_A_CDC_CONN_EQ1_B2_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_EQ1_B3_CTL (0x5B0)
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#define MSM8X10_WCD_A_CDC_CONN_EQ1_B3_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_EQ1_B4_CTL (0x5B4)
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#define MSM8X10_WCD_A_CDC_CONN_EQ1_B4_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_EQ2_B1_CTL (0x5B8)
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#define MSM8X10_WCD_A_CDC_CONN_EQ2_B1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_EQ2_B2_CTL (0x5BC)
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#define MSM8X10_WCD_A_CDC_CONN_EQ2_B2_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_EQ2_B3_CTL (0x5C0)
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#define MSM8X10_WCD_A_CDC_CONN_EQ2_B3_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_EQ2_B4_CTL (0x5C4)
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#define MSM8X10_WCD_A_CDC_CONN_EQ2_B4_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_CONN_TX_I2S_SD1_CTL (0x5C8)
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#define MSM8X10_WCD_A_CDC_CONN_TX_I2S_SD1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_TOP_GAIN_UPDATE (0x5D0)
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#define MSM8X10_WCD_A_CDC_TOP_GAIN_UPDATE__POR (0x00)
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#define MSM8X10_WCD_A_CDC_TOP_CTL (0x5D8)
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#define MSM8X10_WCD_A_CDC_TOP_CTL__POR (0x01)
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#define MSM8X10_WCD_A_CDC_DEBUG_DESER1_CTL (0x5E0)
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#define MSM8X10_WCD_A_CDC_DEBUG_DESER1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_DEBUG_DESER2_CTL (0x5E4)
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#define MSM8X10_WCD_A_CDC_DEBUG_DESER2_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_DEBUG_B1_CTL (0x5E8)
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#define MSM8X10_WCD_A_CDC_DEBUG_B1_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_DEBUG_B2_CTL (0x5EC)
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#define MSM8X10_WCD_A_CDC_DEBUG_B2_CTL__POR (0x00)
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#define MSM8X10_WCD_A_CDC_DEBUG_B3_CTL (0x5F0)
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#define MSM8X10_WCD_A_CDC_DEBUG_B3_CTL__POR (0x00)
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#endif
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