mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-10-31 18:09:19 +00:00
fdca21ad46
CONFIG_HOTPLUG is going away as an option. As result the __dev* markings will be going away. Remove use of __devinit, __devexit_p, __devinitdata, __devinitconst, and __devexit. Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
196 lines
4.8 KiB
C
196 lines
4.8 KiB
C
/*
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* sound/soc/samsung/smdk_wm8580pcm.c
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*
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* Copyright (c) 2011 Samsung Electronics Co. Ltd
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/module.h>
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#include <sound/soc.h>
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#include <sound/pcm_params.h>
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#include <sound/pcm.h>
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#include <asm/mach-types.h>
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#include "../codecs/wm8580.h"
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#include "dma.h"
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#include "pcm.h"
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/*
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* Board Settings:
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* o '1' means 'ON'
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* o '0' means 'OFF'
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* o 'X' means 'Don't care'
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*
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* SMDK6410, SMDK6440, SMDK6450 Base B/D: CFG1-0000, CFG2-1111
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* SMDKC110, SMDKV210: CFGB11-100100, CFGB12-0000
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*/
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#define SMDK_WM8580_EXT_OSC 12000000
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#define SMDK_WM8580_EXT_MCLK 4096000
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#define SMDK_WM8580_EXT_VOICE 2048000
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static unsigned long mclk_freq;
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static unsigned long xtal_freq;
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/*
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* If MCLK clock directly gets from XTAL, we don't have to use PLL
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* to make MCLK, but if XTAL clock source connects with other codec
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* pin (like XTI), we should have to set codec's PLL to make MCLK.
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* Because Samsung SoC does not support pcmcdclk output like I2S.
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*/
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static int smdk_wm8580_pcm_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_dai *codec_dai = rtd->codec_dai;
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struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
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int rfs, ret;
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switch (params_rate(params)) {
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case 8000:
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break;
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default:
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printk(KERN_ERR "%s:%d Sampling Rate %u not supported!\n",
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__func__, __LINE__, params_rate(params));
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return -EINVAL;
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}
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rfs = mclk_freq / params_rate(params) / 2;
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/* Set the codec DAI configuration */
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ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_B
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| SND_SOC_DAIFMT_IB_NF
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| SND_SOC_DAIFMT_CBS_CFS);
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if (ret < 0)
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return ret;
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/* Set the cpu DAI configuration */
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ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_B
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| SND_SOC_DAIFMT_IB_NF
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| SND_SOC_DAIFMT_CBS_CFS);
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if (ret < 0)
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return ret;
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if (mclk_freq == xtal_freq) {
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ret = snd_soc_dai_set_sysclk(codec_dai, WM8580_CLKSRC_MCLK,
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mclk_freq, SND_SOC_CLOCK_IN);
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if (ret < 0)
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return ret;
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ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_MCLK,
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WM8580_CLKSRC_MCLK);
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if (ret < 0)
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return ret;
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} else {
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ret = snd_soc_dai_set_sysclk(codec_dai, WM8580_CLKSRC_PLLA,
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mclk_freq, SND_SOC_CLOCK_IN);
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if (ret < 0)
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return ret;
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ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_MCLK,
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WM8580_CLKSRC_PLLA);
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if (ret < 0)
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return ret;
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ret = snd_soc_dai_set_pll(codec_dai, WM8580_PLLA, 0,
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xtal_freq, mclk_freq);
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if (ret < 0)
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return ret;
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}
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/* Set PCM source clock on CPU */
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ret = snd_soc_dai_set_sysclk(cpu_dai, S3C_PCM_CLKSRC_MUX,
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mclk_freq, SND_SOC_CLOCK_IN);
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if (ret < 0)
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return ret;
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/* Set SCLK_DIV for making bclk */
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ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C_PCM_SCLK_PER_FS, rfs);
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if (ret < 0)
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return ret;
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return 0;
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}
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static struct snd_soc_ops smdk_wm8580_pcm_ops = {
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.hw_params = smdk_wm8580_pcm_hw_params,
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};
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static struct snd_soc_dai_link smdk_dai[] = {
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{
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.name = "WM8580 PAIF PCM RX",
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.stream_name = "Playback",
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.cpu_dai_name = "samsung-pcm.0",
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.codec_dai_name = "wm8580-hifi-playback",
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.platform_name = "samsung-audio",
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.codec_name = "wm8580.0-001b",
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.ops = &smdk_wm8580_pcm_ops,
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}, {
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.name = "WM8580 PAIF PCM TX",
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.stream_name = "Capture",
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.cpu_dai_name = "samsung-pcm.0",
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.codec_dai_name = "wm8580-hifi-capture",
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.platform_name = "samsung-pcm.0",
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.codec_name = "wm8580.0-001b",
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.ops = &smdk_wm8580_pcm_ops,
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},
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};
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static struct snd_soc_card smdk_pcm = {
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.name = "SMDK-PCM",
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.owner = THIS_MODULE,
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.dai_link = smdk_dai,
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.num_links = 2,
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};
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/*
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* After SMDKC110 Base Board's Rev is '0.1', 12MHz External OSC(X1)
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* is absent (or not connected), so we connect EXT_VOICE_CLK(OSC4),
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* 2.0484Mhz, directly with MCLK both Codec and SoC.
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*/
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static int snd_smdk_probe(struct platform_device *pdev)
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{
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int ret = 0;
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xtal_freq = SMDK_WM8580_EXT_OSC;
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mclk_freq = SMDK_WM8580_EXT_MCLK;
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if (machine_is_smdkc110() || machine_is_smdkv210())
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xtal_freq = mclk_freq = SMDK_WM8580_EXT_VOICE;
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smdk_pcm.dev = &pdev->dev;
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ret = snd_soc_register_card(&smdk_pcm);
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if (ret) {
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dev_err(&pdev->dev, "snd_soc_register_card failed %d\n", ret);
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return ret;
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}
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return 0;
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}
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static int snd_smdk_remove(struct platform_device *pdev)
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{
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snd_soc_unregister_card(&smdk_pcm);
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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static struct platform_driver snd_smdk_driver = {
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.driver = {
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.owner = THIS_MODULE,
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.name = "samsung-smdk-pcm",
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},
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.probe = snd_smdk_probe,
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.remove = snd_smdk_remove,
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};
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module_platform_driver(snd_smdk_driver);
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MODULE_AUTHOR("Sangbeom Kim, <sbkim73@samsung.com>");
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MODULE_DESCRIPTION("ALSA SoC SMDK WM8580 for PCM");
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MODULE_LICENSE("GPL");
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