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3440df24e7
This is a combination of 13 commits.
commit 59a27ca89fb515caeac2b97059832515566f70d9
Author: John Howe <jhowe@codeaurora.org>
Date: Tue Jan 4 17:18:54 2011 -0500
hw_random: Add Qualcomm MSM random number driver
This driver uses the hardware random number generator on MSM chips.
Change-Id: I13b4d831fb9b5487356af466536a9005107ff723
Signed-off-by: John Howe <jhowe@codeaurora.org>
commit 09cae33a80706e0aa77bdc4e1b493ef2a36dbbde
Author: John Howe <jhowe@codeaurora.org>
Date: Fri Jan 14 10:21:05 2011 -0500
hw_random: add PRNG clock control
Change-Id: I6d9dd2ee7c50020fb8d41242b655e172e4c9eff2
Signed-off-by: John Howe <jhowe@codeaurora.org>
commit 0573eda3ce19c01825ded4fe850362c37460dc20
Author: John Howe <jhowe@codeaurora.org>
Date: Mon Jan 24 14:56:06 2011 -0500
hw_random: remove clk frequency control
The clock only supports one rate, 64MHz, and is set to that
rate by default.
Change-Id: I820c74e44f4ebdec7b891a4c89d681cb5c3dcee6
Signed-off-by: John Howe <jhowe@codeaurora.org>
commit fab0a4d40e18be4a31a4720acafb128893c620e8
Author: John Howe <jhowe@codeaurora.org>
Date: Tue Apr 12 14:48:51 2011 -0400
hw_random: Use memory barriers
Change-Id: Ie216141d7f6997266d8c5ed4bbd436f1be6551b8
Signed-off-by: John Howe <jhowe@codeaurora.org>
commit f07f1ba547790155db4c508ccfa58b64c967fe8e
Author: Raj Kushwaha <rajk@codeaurora.org>
Date: Tue Jul 26 14:35:28 2011 -0700
hw_random: msm: Remove PRNG hardware configuration
LSFR and CONFIG registers are configured by secure domain
code and XPU protected.
CRs-Fixed: 284133
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
(cherry picked from commit a4f802b0f5d0faee9e83020c599b2f4b0b27de5f)
Change-Id: Ie73cc3a95d1e2fff970e4d71f15fc1cbb4ead11c
Signed-off-by: Raj Kushwaha <rajk@codeaurora.org>
commit 26cef0c9d572e55df0f17dc4a5de380595eddaeb
Author: Matt Wagantall <mattw@codeaurora.org>
Date: Thu Aug 11 17:19:31 2011 -0700
msm: clock: Use device names to distinguish between PRNG clocks
Drivers should now use their device names to distinguish between
clocks of the same type rather than the clock name. This allows
the clock names to be updated to match the new naming convention.
Change-Id: Ibf00fd3d406adb04299e3e79e379d4fefe70f2b4
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
commit 5ad373931744ae98289ec680334d7cc0bee1c0b6
Author: Ramesh Masavarapu <rameshm@codeaurora.org>
Date: Mon Oct 10 10:44:10 2011 -0700
msm: Add PRNG to MSM9615 device.
Add configuration parameters for MSM9615 device.
PRNG hardware registers initialization in msm_rng.c is done
currently for MSM9615.
Change-Id: I2a05e9e582ce94a25bec71e1acaee95d62cd9469
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
commit 2f963dbc78c6c0703f51466b2b242287a2df5487
Author: Ramesh Masavarapu <rameshm@codeaurora.org>
Date: Thu Oct 20 15:33:50 2011 -0700
msm: Removed target specific changes for enabling PRNG h/w.
The driver checks if the PRNG h/w is enabled. If it is not ON, it
enables the PRNG h/w.
Change-Id: I7c73eba7ba47f4fca116cfe0884758e6dd130ed0
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
commit 46af59fb8f4bce302ad4d787b63b25e46548df6a
Author: Stepan Moskovchenko <stepanm@codeaurora.org>
Date: Tue Feb 7 14:38:59 2012 -0800
msm: rng: Disable RNG init on APQ8064
Change-Id: Ic42a85c51faea8a17b02eb4987d0f5db732716c2
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
commit a54263b0056b15cad1336a33d57bb1db013e8abb
Author: Ramesh Masavarapu <rameshm@codeaurora.org>
Date: Wed Feb 1 22:49:01 2012 -0800
msm: Removed XPU violations.
During initialization, there is a violation in writing to
"read only" registers for targets that support trust zone.
Trustzone marks certain registers as read-only.
This change fixes the issue by writing to registers only
on targets that do not support trust zone.
Change-Id: I69bb0f1bad199201aa3dd8b378ca1683dfa81c86
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
commit a99fcc24e94481134ca22f9778e88ed31646d6e3
Author: Ramesh Masavarapu <rameshm@codeaurora.org>
Date: Wed Feb 22 14:30:32 2012 -0800
Revert "msm: rng: Disable RNG init on APQ8064"
This reverts commit 46af59fb8f4bce302ad4d787b63b25e46548df6a.
The RNG driver was initially disabled because of missing clock
changes and this driver was causing boot up issues.
Now with the clock changes checked in the RNG driver works.
Change-Id: I127f25c8be6b715510c1fb16b274a814416d8a8a
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
commit 801c392ab9ee2893c6f3ca506e43afa62798890b
Author: Ramesh Masavarapu <rameshm@codeaurora.org>
Date: Tue Apr 24 16:28:00 2012 -0700
prng: Replace clk_enable and clk_disable APIs.
The clk driver has introduced new clock APIs that replace
the existing clk_enable and clk_disable.
-clk_enable() APIs is replaced with clk_prepare_enable().
-clk_disable() API is replaced with clk_disable_unprepare().
Change-Id: Ib6c452e7dc3f357497eae5a9302a7352a19fcb18
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
commit de991f08a8738dc66e65488aebed472de65ce237
Author: Hariprasad Dhalinarasimha <hnamgund@codeaurora.org>
Date: Thu May 31 13:15:51 2012 -0700
PRNG: Device tree entry for qrng device.
Cleanup platorm device entry & add device tree entry
Change-Id: I5bde944d63276a3aaf00b7415066963027f11249
Signed-off-by: Hariprasad Dhalinarasimha <hnamgund@codeaurora.org>
commit a4100a4a6e2a1843645d3eff22dabb387d4cbb61
Author: Stephen Boyd <sboyd@codeaurora.org>
Date: Mon Jun 25 15:48:37 2012 -0700
msm-rng: Fix PRNG_LFSR_CFG setup
Changes to only configure the LFSR on devices that don't have the
prng hardware already setup mistakenly removed the LFSR
configuration. Instead, the change is ORing in 1s into the top 16
bits of the register (they're marked as reserved).
Restore the original code by masking off the lower 16 bits of the
register and filling them with values from the
PRNG_LFSR_CFG_CLOCKS define.
Change-Id: Idd0df7b49175c211eec5ea778733ae81f5bc8188
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
commit 0bef6ede4b779c19091234e20ecfbb76a44edac0
Author: Hariprasad Dhalinarasimha <hnamgund@codeaurora.org>
Date: Wed Nov 7 19:47:21 2012 -0800
msm: rng: Add support for iface clk
Currently the driver supports only enabling core_clk,but on
certain targets, iface_clk is used for the hardware RNG
block. This fix adds compatibility to targets that have iface
clock instead of the core clock.
Change-Id: I480c3c7070e09f945439ea48e6877c7170ceeeb9
Signed-off-by: Hariprasad Dhalinarasimha <hnamgund@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Introduction:
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=============
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The msm_rng device driver handles random number generation
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using hardware present in MSM chipsets.
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Hardware description:
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=====================
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The supported hardware is a macro block within a system-on-a-chip (SoC).
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The hardware is pseudo random number generator (PRNG) with four oscillators
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setup with a linear feedback shift register (LFSR).
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The hardware must be initially configured once for normal operation and
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a 32bit FIFO is read to obtain hardware generated pseudo random numbers.
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Currently the driver configures the hardware registers during initialization
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and the future plan is to have the boot loader configure these registers and
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write lock them so only host OS can read them and the driver writes will be
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ignored.
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Software description
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====================
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The driver is based on the platform_driver model. It registers an entry,
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exit and probe functions. Once the probe function is called, the driver
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registers a callback function with the hwrng (Hardware Random Number Generator)
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subsystem that is called when the hardware device (i.e. /dev/hw_random) is
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requesting random data from this device.
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Once the callback is issued from the hwrng subsystem, the driver checks to
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make sure the hardware has random data available and determines the maximum
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data it can return and returns that much data back.
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Power Management
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================
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Initially, no services are provided in the area of power management.
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SMP/multi-core
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==============
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The locking mechanism for the hwrng operations is taken care of by the hwrng
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framework. There are no SMP situations within the driver that need addressing.
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Driver parameters
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=================
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This driver is built and statically linked into the kernel; therefore,
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there are no module parameters supported by this driver.
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There are no kernel command line parameters supported by this driver.
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Config options
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==============
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This driver is enabled by the kernel config option CONFIG_HW_RANDOM_MSM.
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The option CONFIG_HW_RANDOM_MSM depends on HW_RANDOM && ARCH_MSM.
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Dependencies:
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=============
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This driver depends on the HW_RANDOM subsystem to register with and get
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callbacks to request random data.
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User space utilities:
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=====================
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The driver alone does not feed random numbers into kernel but just provides a
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method to get random numbers to a known device (i.e. /dev/hw_random). A user-
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space utility is required to monitor the /dev/random device entropy pool and
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feed it from the /dev/hw_random device. This application also must perform some
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sort of sanity checking on the returned data to make sure the data is not all
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the same.
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There is currently a GPL v2 tool called rng-tools that has a daemon called,
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"rngd" that performs this functionality. There is also a test tool in this
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package that tests the whole random subsystem.
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