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https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
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0b29de4a6a
Add macros to enable and disable access to CP6. On the iop3xx, enabling CP6 access unfortunately also enables access to that coprocessor from unprivileged code, so we need these macros to enable and disable access to the coprocessor whenever we need to access it. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
166 lines
6.7 KiB
C
166 lines
6.7 KiB
C
/*
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* include/asm-arm/hardware/iop3xx.h
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*
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* Intel IOP32X and IOP33X register definitions
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*
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* Author: Rory Bolt <rorybolt@pacbell.net>
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* Copyright (C) 2002 Rory Bolt
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* Copyright (C) 2004 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __IOP3XX_H
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#define __IOP3XX_H
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/*
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* IOP3XX processor registers
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*/
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#define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000
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#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfeffe000
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#define IOP3XX_PERIPHERAL_SIZE 0x00002000
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#define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
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/* Address Translation Unit */
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#define IOP3XX_ATUVID (volatile u16 *)IOP3XX_REG_ADDR(0x0100)
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#define IOP3XX_ATUDID (volatile u16 *)IOP3XX_REG_ADDR(0x0102)
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#define IOP3XX_ATUCMD (volatile u16 *)IOP3XX_REG_ADDR(0x0104)
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#define IOP3XX_ATUSR (volatile u16 *)IOP3XX_REG_ADDR(0x0106)
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#define IOP3XX_ATURID (volatile u8 *)IOP3XX_REG_ADDR(0x0108)
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#define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
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#define IOP3XX_ATUCLSR (volatile u8 *)IOP3XX_REG_ADDR(0x010c)
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#define IOP3XX_ATULT (volatile u8 *)IOP3XX_REG_ADDR(0x010d)
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#define IOP3XX_ATUHTR (volatile u8 *)IOP3XX_REG_ADDR(0x010e)
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#define IOP3XX_ATUBIST (volatile u8 *)IOP3XX_REG_ADDR(0x010f)
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#define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
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#define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
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#define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
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#define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
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#define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
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#define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
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#define IOP3XX_ASVIR (volatile u16 *)IOP3XX_REG_ADDR(0x012c)
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#define IOP3XX_ASIR (volatile u16 *)IOP3XX_REG_ADDR(0x012e)
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#define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
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#define IOP3XX_ATUILR (volatile u8 *)IOP3XX_REG_ADDR(0x013c)
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#define IOP3XX_ATUIPR (volatile u8 *)IOP3XX_REG_ADDR(0x013d)
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#define IOP3XX_ATUMGNT (volatile u8 *)IOP3XX_REG_ADDR(0x013e)
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#define IOP3XX_ATUMLAT (volatile u8 *)IOP3XX_REG_ADDR(0x013f)
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#define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
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#define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144)
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#define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148)
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#define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c)
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#define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150)
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#define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154)
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#define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158)
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#define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c)
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#define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160)
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#define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164)
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#define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168)
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#define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c)
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#define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178)
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#define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180)
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#define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184)
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#define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188)
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#define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c)
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#define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190)
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#define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194)
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#define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198)
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#define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c)
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#define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
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#define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
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#define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
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#define IOP3XX_PMCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01c0)
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#define IOP3XX_PMNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01c1)
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#define IOP3XX_APMCR (volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
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#define IOP3XX_APMCSR (volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
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#define IOP3XX_PCIXCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01e0)
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#define IOP3XX_PCIXNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01e1)
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#define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
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#define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
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#define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
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/* Timers */
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#define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000)
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#define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004)
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#define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008)
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#define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c)
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#define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010)
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#define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014)
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#define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018)
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#define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c)
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#define IOP3XX_TMR_TC 0x01
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#define IOP3XX_TMR_EN 0x02
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#define IOP3XX_TMR_RELOAD 0x04
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#define IOP3XX_TMR_PRIVILEGED 0x09
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#define IOP3XX_TMR_RATIO_1_1 0x00
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#define IOP3XX_TMR_RATIO_4_1 0x10
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#define IOP3XX_TMR_RATIO_8_1 0x20
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#define IOP3XX_TMR_RATIO_16_1 0x30
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/* I2C bus interface unit */
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#define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
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#define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684)
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#define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688)
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#define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c)
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#define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694)
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#define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
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#define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
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#define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
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#define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
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#define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
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/*
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* IOP3XX I/O and Mem space regions for PCI autoconfiguration
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*/
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#define IOP3XX_PCI_MEM_WINDOW_SIZE 0x04000000
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#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
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#define IOP3XX_PCI_LOWER_MEM_BA (*IOP3XX_OMWTVR0)
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#define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000
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#define IOP3XX_PCI_LOWER_IO_PA 0x90000000
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#define IOP3XX_PCI_LOWER_IO_VA 0xfe000000
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#define IOP3XX_PCI_LOWER_IO_BA (*IOP3XX_OIOWTVR)
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#ifndef __ASSEMBLY__
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void iop3xx_map_io(void);
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void iop3xx_init_time(unsigned long);
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unsigned long iop3xx_gettimeoffset(void);
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extern struct platform_device iop3xx_i2c0_device;
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extern struct platform_device iop3xx_i2c1_device;
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extern inline void iop3xx_cp6_enable(void)
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{
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u32 temp;
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asm volatile (
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"mrc p15, 0, %0, c15, c1, 0\n\t"
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"orr %0, %0, #(1 << 6)\n\t"
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"mcr p15, 0, %0, c15, c1, 0\n\t"
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"mrc p15, 0, %0, c15, c1, 0\n\t"
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"mov %0, %0\n\t"
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"sub pc, pc, #4\n\t"
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: "=r" (temp) );
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}
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extern inline void iop3xx_cp6_disable(void)
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{
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u32 temp;
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asm volatile (
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"mrc p15, 0, %0, c15, c1, 0\n\t"
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"bic %0, %0, #(1 << 6)\n\t"
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"mcr p15, 0, %0, c15, c1, 0\n\t"
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"mrc p15, 0, %0, c15, c1, 0\n\t"
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"mov %0, %0\n\t"
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"sub pc, pc, #4\n\t"
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: "=r" (temp) );
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}
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#endif
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#endif
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