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0d72ba930c
Some versions of PWRficient 1682M have an interrupt controller in which the first register in each pair for interrupt sources doesn't always read with the right polarity/sense values. To work around this, keep a software copy of the register instead. Since it's not modified from the mpic itself, it's a feasible solution. Still, keep it under a config option to avoid wasting memory on other platforms. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
38 lines
842 B
Text
38 lines
842 B
Text
config PPC_PASEMI
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depends on PPC_MULTIPLATFORM && PPC64
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bool "PA Semi SoC-based platforms"
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default n
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select MPIC
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select PPC_UDBG_16550
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select PPC_NATIVE
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select MPIC_BROKEN_REGREAD
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help
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This option enables support for PA Semi's PWRficient line
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of SoC processors, including PA6T-1682M
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menu "PA Semi PWRficient options"
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depends on PPC_PASEMI
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config PPC_PASEMI_IOMMU
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bool "PA Semi IOMMU support"
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depends on PPC_PASEMI
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help
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IOMMU support for PA6T-1682M
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config PPC_PASEMI_MDIO
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depends on PHYLIB
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tristate "MDIO support via GPIO"
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default y
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help
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Driver for MDIO via GPIO on PWRficient platforms
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config ELECTRA_IDE
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tristate "Electra IDE driver"
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default y
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depends on PPC_PASEMI && ATA
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select PATA_PLATFORM
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help
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This includes driver support for the Electra on-board IDE
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interface.
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endmenu
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