300 lines
6.8 KiB
C
300 lines
6.8 KiB
C
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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* Copyright (c) 2013 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* MSM ARMv8 CPU Operations
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* Based on arch/arm64/kernel/smp_spin_table.c
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*/
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#include <linux/bitops.h>
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#include <linux/cpu.h>
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#include <linux/cpumask.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/smp.h>
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#include <soc/qcom/cpu_pwr_ctl.h>
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#include <soc/qcom/scm-boot.h>
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#include <soc/qcom/socinfo.h>
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#include <soc/qcom/pm.h>
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#include <soc/qcom/spm.h>
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#include <soc/qcom/jtag.h>
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#include <asm/barrier.h>
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#include <asm/cacheflush.h>
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#include <asm/cpu_ops.h>
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#include <asm/cputype.h>
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#include <asm/smp_plat.h>
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static DEFINE_RAW_SPINLOCK(boot_lock);
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DEFINE_PER_CPU(int, cold_boot_done);
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static int cold_boot_flags[] = {
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0,
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SCM_FLAG_COLDBOOT_CPU1,
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SCM_FLAG_COLDBOOT_CPU2,
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SCM_FLAG_COLDBOOT_CPU3,
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};
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static void write_pen_release(u64 val)
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{
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void *start = (void *)&secondary_holding_pen_release;
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unsigned long size = sizeof(secondary_holding_pen_release);
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secondary_holding_pen_release = val;
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smp_wmb();
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__flush_dcache_area(start, size);
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}
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static int secondary_pen_release(unsigned int cpu)
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{
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unsigned long timeout;
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/*
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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raw_spin_lock(&boot_lock);
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write_pen_release(cpu_logical_map(cpu));
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/*
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* Wake-up cpu with am IPI
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*/
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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if (secondary_holding_pen_release == INVALID_HWID)
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break;
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udelay(10);
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}
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raw_spin_unlock(&boot_lock);
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return secondary_holding_pen_release != INVALID_HWID ? -ENOSYS : 0;
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}
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static int __init msm_cpu_init(struct device_node *dn, unsigned int cpu)
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{
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return 0;
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}
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static int __init msm_cpu_prepare(unsigned int cpu)
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{
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u64 mpidr_el1 = cpu_logical_map(cpu);
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if (scm_is_mc_boot_available()) {
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if (mpidr_el1 & ~MPIDR_HWID_BITMASK) {
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pr_err("CPU%d:Failed to set boot address\n", cpu);
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return -ENOSYS;
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}
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if (scm_set_boot_addr_mc(virt_to_phys(secondary_holding_pen),
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BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 0)),
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BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 1)),
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BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 2)),
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SCM_FLAG_COLDBOOT_MC)) {
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pr_warn("CPU%d:Failed to set boot address\n", cpu);
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return -ENOSYS;
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}
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} else {
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if (scm_set_boot_addr(virt_to_phys(secondary_holding_pen),
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cold_boot_flags[cpu])) {
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pr_warn("Failed to set CPU %u boot address\n", cpu);
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return -ENOSYS;
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}
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}
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/* Mark CPU0 cold boot flag as done */
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if (per_cpu(cold_boot_done, 0) == false)
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per_cpu(cold_boot_done, 0) = true;
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return 0;
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}
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static int __init msm8976_cpu_prepare(unsigned int cpu)
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{
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int ret;
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u32 mpidr = cpu_logical_map(cpu);
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if ((per_cpu(cold_boot_done, 0) == false)
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&& MPIDR_AFFINITY_LEVEL(mpidr, 1)) {
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ret = msm8976_cpu_ldo_config(0);
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if (ret)
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return ret;
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}
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return msm_cpu_prepare(cpu);
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}
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static int __init msm8994_cpu_prepare(unsigned int cpu)
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{
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int ret;
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if (per_cpu(cold_boot_done, 0) == false) {
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ret = msm8994_cpu_ldo_config(0);
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if (ret)
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return ret;
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}
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return msm_cpu_prepare(cpu);
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}
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static int msm_cpu_boot(unsigned int cpu)
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{
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int ret = 0;
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if (per_cpu(cold_boot_done, cpu) == false) {
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if (of_board_is_sim()) {
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ret = msm_unclamp_secondary_arm_cpu_sim(cpu);
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if (ret)
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return ret;
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} else {
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ret = msm_unclamp_secondary_arm_cpu(cpu);
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if (ret)
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return ret;
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}
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per_cpu(cold_boot_done, cpu) = true;
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}
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return secondary_pen_release(cpu);
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}
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static int msm8976_cpu_boot(unsigned int cpu)
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{
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int ret = 0;
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u32 mpidr = cpu_logical_map(cpu);
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if (per_cpu(cold_boot_done, cpu) == false) {
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if (of_board_is_sim()) {
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ret = msm_unclamp_secondary_arm_cpu_sim(cpu);
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if (ret)
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return ret;
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} else {
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ret = msm8976_unclamp_secondary_arm_cpu(cpu);
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if (ret)
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return ret;
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}
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if (MPIDR_AFFINITY_LEVEL(mpidr, 1)) {
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ret = msm8976_cpu_ldo_config(cpu);
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if (ret)
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return ret;
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}
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per_cpu(cold_boot_done, cpu) = true;
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}
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return secondary_pen_release(cpu);
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}
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static int msm8994_cpu_boot(unsigned int cpu)
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{
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int ret = 0;
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if (per_cpu(cold_boot_done, cpu) == false) {
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if (of_board_is_sim()) {
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ret = msm_unclamp_secondary_arm_cpu_sim(cpu);
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if (ret)
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return ret;
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} else {
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ret = msm8994_unclamp_secondary_arm_cpu(cpu);
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if (ret)
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return ret;
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}
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ret = msm8994_cpu_ldo_config(cpu);
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if (ret)
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return ret;
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per_cpu(cold_boot_done, cpu) = true;
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}
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return secondary_pen_release(cpu);
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}
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void msm_cpu_postboot(void)
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{
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msm_jtag_restore_state();
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/*
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* Let the primary processor know we're out of the pen.
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*/
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write_pen_release(INVALID_HWID);
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msm_spm_set_low_power_mode(MSM_SPM_MODE_CLOCK_GATING, false);
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/*
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* Synchronise with the boot thread.
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*/
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raw_spin_lock(&boot_lock);
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raw_spin_unlock(&boot_lock);
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static void msm_wfi_cpu_die(unsigned int cpu)
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{
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if (unlikely(cpu != smp_processor_id())) {
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pr_crit("%s: running on %u, should be %u\n",
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__func__, smp_processor_id(), cpu);
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BUG();
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}
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for (;;) {
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lpm_cpu_hotplug_enter(cpu);
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if (secondary_holding_pen_release == cpu_logical_map(cpu)) {
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/*Proper wake up */
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break;
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}
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pr_debug("CPU%u: spurious wakeup call\n", cpu);
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BUG();
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}
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}
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#endif
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static const struct cpu_operations msm_cortex_a_ops = {
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.name = "qcom,arm-cortex-acc",
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.cpu_init = msm_cpu_init,
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.cpu_prepare = msm_cpu_prepare,
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.cpu_boot = msm_cpu_boot,
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.cpu_postboot = msm_cpu_postboot,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = msm_wfi_cpu_die,
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#endif
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.cpu_suspend = msm_pm_collapse,
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};
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CPU_METHOD_OF_DECLARE(msm_cortex_a_ops, &msm_cortex_a_ops);
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static const struct cpu_operations msm8994_cortex_a_ops = {
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.name = "qcom,8994-arm-cortex-acc",
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.cpu_init = msm_cpu_init,
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.cpu_prepare = msm8994_cpu_prepare,
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.cpu_boot = msm8994_cpu_boot,
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.cpu_postboot = msm_cpu_postboot,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = msm_wfi_cpu_die,
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#endif
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.cpu_suspend = msm_pm_collapse,
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};
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CPU_METHOD_OF_DECLARE(msm8994_cortex_a_ops, &msm8994_cortex_a_ops);
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static const struct cpu_operations msm8976_cortex_a_ops = {
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.name = "qcom,8976-arm-cortex-acc",
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.cpu_init = msm_cpu_init,
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.cpu_prepare = msm8976_cpu_prepare,
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.cpu_boot = msm8976_cpu_boot,
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.cpu_postboot = msm_cpu_postboot,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = msm_wfi_cpu_die,
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#endif
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#ifdef CONFIG_ARM64_CPU_SUSPEND
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.cpu_suspend = msm_pm_collapse,
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#endif
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};
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CPU_METHOD_OF_DECLARE(msm8976_cortex_a_ops, &msm8976_cortex_a_ops);
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