mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-09-21 03:43:03 +00:00
b2b708cf2f
commit e6b8fd028b584ffca7a7255b8971f254932c9fce upstream.
We can't take an IRQ when we're about to do a trechkpt as our GPR state is set
to user GPR values.
We've hit this when running some IBM Java stress tests in the lab resulting in
the following dump:
cpu 0x3f: Vector: 700 (Program Check) at [c000000007eb3d40]
pc: c000000000050074: restore_gprs+0xc0/0x148
lr: 00000000b52a8184
sp: ac57d360
msr: 8000000100201030
current = 0xc00000002c500000
paca = 0xc000000007dbfc00 softe: 0 irq_happened: 0x00
pid = 34535, comm = Pooled Thread #
R00 = 00000000b52a8184 R16 = 00000000b3e48fda
R01 = 00000000ac57d360 R17 = 00000000ade79bd8
R02 = 00000000ac586930 R18 = 000000000fac9bcc
R03 = 00000000ade60000 R19 = 00000000ac57f930
R04 = 00000000f6624918 R20 = 00000000ade79be8
R05 = 00000000f663f238 R21 = 00000000ac218a54
R06 = 0000000000000002 R22 = 000000000f956280
R07 = 0000000000000008 R23 = 000000000000007e
R08 = 000000000000000a R24 = 000000000000000c
R09 = 00000000b6e69160 R25 = 00000000b424cf00
R10 = 0000000000000181 R26 = 00000000f66256d4
R11 = 000000000f365ec0 R27 = 00000000b6fdcdd0
R12 = 00000000f66400f0 R28 = 0000000000000001
R13 = 00000000ada71900 R29 = 00000000ade5a300
R14 = 00000000ac2185a8 R30 = 00000000f663f238
R15 = 0000000000000004 R31 = 00000000f6624918
pc = c000000000050074 restore_gprs+0xc0/0x148
cfar= c00000000004fe28 dont_restore_vec+0x1c/0x1a4
lr = 00000000b52a8184
msr = 8000000100201030 cr = 24804888
ctr = 0000000000000000 xer = 0000000000000000 trap = 700
This moves tm_recheckpoint to a C function and moves the tm_restore_sprs into
that function. It then adds IRQ disabling over the trechkpt critical section.
It also sets the TEXASR FS in the signals code to ensure this is never set now
that we explictly write the TM sprs in tm_recheckpoint.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
443 lines
11 KiB
ArmAsm
443 lines
11 KiB
ArmAsm
/*
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* Transactional memory support routines to reclaim and recheckpoint
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* transactional process state.
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*
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* Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
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*/
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#include <asm/asm-offsets.h>
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#include <asm/ppc_asm.h>
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#include <asm/ppc-opcode.h>
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#include <asm/ptrace.h>
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#include <asm/reg.h>
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#ifdef CONFIG_VSX
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/* See fpu.S, this is very similar but to save/restore checkpointed FPRs/VSRs */
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#define __SAVE_32FPRS_VSRS_TRANSACT(n,c,base) \
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BEGIN_FTR_SECTION \
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b 2f; \
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END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
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SAVE_32FPRS_TRANSACT(n,base); \
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b 3f; \
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2: SAVE_32VSRS_TRANSACT(n,c,base); \
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3:
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/* ...and this is just plain borrowed from there. */
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#define __REST_32FPRS_VSRS(n,c,base) \
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BEGIN_FTR_SECTION \
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b 2f; \
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END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
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REST_32FPRS(n,base); \
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b 3f; \
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2: REST_32VSRS(n,c,base); \
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3:
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#else
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#define __SAVE_32FPRS_VSRS_TRANSACT(n,c,base) SAVE_32FPRS_TRANSACT(n, base)
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#define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base)
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#endif
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#define SAVE_32FPRS_VSRS_TRANSACT(n,c,base) \
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__SAVE_32FPRS_VSRS_TRANSACT(n,__REG_##c,__REG_##base)
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#define REST_32FPRS_VSRS(n,c,base) \
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__REST_32FPRS_VSRS(n,__REG_##c,__REG_##base)
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/* Stack frame offsets for local variables. */
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#define TM_FRAME_L0 TM_FRAME_SIZE-16
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#define TM_FRAME_L1 TM_FRAME_SIZE-8
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#define STACK_PARAM(x) (48+((x)*8))
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/* In order to access the TM SPRs, TM must be enabled. So, do so: */
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_GLOBAL(tm_enable)
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mfmsr r4
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li r3, MSR_TM >> 32
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sldi r3, r3, 32
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and. r0, r4, r3
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bne 1f
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or r4, r4, r3
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mtmsrd r4
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1: blr
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_GLOBAL(tm_save_sprs)
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mfspr r0, SPRN_TFHAR
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std r0, THREAD_TM_TFHAR(r3)
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mfspr r0, SPRN_TEXASR
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std r0, THREAD_TM_TEXASR(r3)
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mfspr r0, SPRN_TFIAR
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std r0, THREAD_TM_TFIAR(r3)
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blr
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_GLOBAL(tm_restore_sprs)
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ld r0, THREAD_TM_TFHAR(r3)
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mtspr SPRN_TFHAR, r0
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ld r0, THREAD_TM_TEXASR(r3)
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mtspr SPRN_TEXASR, r0
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ld r0, THREAD_TM_TFIAR(r3)
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mtspr SPRN_TFIAR, r0
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blr
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/* Passed an 8-bit failure cause as first argument. */
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_GLOBAL(tm_abort)
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TABORT(R3)
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blr
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.section ".toc","aw"
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DSCR_DEFAULT:
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.tc dscr_default[TC],dscr_default
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.section ".text"
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/* void tm_reclaim(struct thread_struct *thread,
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* unsigned long orig_msr,
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* uint8_t cause)
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*
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* - Performs a full reclaim. This destroys outstanding
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* transactions and updates thread->regs.tm_ckpt_* with the
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* original checkpointed state. Note that thread->regs is
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* unchanged.
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* - FP regs are written back to thread->transact_fpr before
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* reclaiming. These are the transactional (current) versions.
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*
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* Purpose is to both abort transactions of, and preserve the state of,
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* a transactions at a context switch. We preserve/restore both sets of process
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* state to restore them when the thread's scheduled again. We continue in
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* userland as though nothing happened, but when the transaction is resumed
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* they will abort back to the checkpointed state we save out here.
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*
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* Call with IRQs off, stacks get all out of sync for some periods in here!
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*/
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_GLOBAL(tm_reclaim)
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mfcr r6
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mflr r0
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std r6, 8(r1)
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std r0, 16(r1)
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std r2, 40(r1)
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stdu r1, -TM_FRAME_SIZE(r1)
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/* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */
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std r3, STACK_PARAM(0)(r1)
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SAVE_NVGPRS(r1)
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mfmsr r14
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mr r15, r14
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ori r15, r15, MSR_FP
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oris r15, r15, MSR_VEC@h
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#ifdef CONFIG_VSX
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BEGIN_FTR_SECTION
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oris r15,r15, MSR_VSX@h
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END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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#endif
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mtmsrd r15
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std r14, TM_FRAME_L0(r1)
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/* Stash the stack pointer away for use after reclaim */
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std r1, PACAR1(r13)
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/* ******************** FPR/VR/VSRs ************
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* Before reclaiming, capture the current/transactional FPR/VR
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* versions /if used/.
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*
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* (If VSX used, FP and VMX are implied. Or, we don't need to look
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* at MSR.VSX as copying FP regs if .FP, vector regs if .VMX covers it.)
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*
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* We're passed the thread's MSR as parameter 2.
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*
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* We enabled VEC/FP/VSX in the msr above, so we can execute these
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* instructions!
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*/
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andis. r0, r4, MSR_VEC@h
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beq dont_backup_vec
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SAVE_32VRS_TRANSACT(0, r6, r3) /* r6 scratch, r3 thread */
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mfvscr vr0
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li r6, THREAD_TRANSACT_VSCR
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stvx vr0, r3, r6
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mfspr r0, SPRN_VRSAVE
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std r0, THREAD_TRANSACT_VRSAVE(r3)
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dont_backup_vec:
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andi. r0, r4, MSR_FP
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beq dont_backup_fp
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SAVE_32FPRS_VSRS_TRANSACT(0, R6, R3) /* r6 scratch, r3 thread */
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mffs fr0
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stfd fr0,THREAD_TRANSACT_FPSCR(r3)
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dont_backup_fp:
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/* The moment we treclaim, ALL of our GPRs will switch
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* to user register state. (FPRs, CCR etc. also!)
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* Use an sprg and a tm_scratch in the PACA to shuffle.
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*/
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TRECLAIM(R5) /* Cause in r5 */
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/* ******************** GPRs ******************** */
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/* Stash the checkpointed r13 away in the scratch SPR and get the real
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* paca
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*/
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SET_SCRATCH0(r13)
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GET_PACA(r13)
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/* Stash the checkpointed r1 away in paca tm_scratch and get the real
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* stack pointer back
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*/
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std r1, PACATMSCRATCH(r13)
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ld r1, PACAR1(r13)
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/* Store the PPR in r11 and reset to decent value */
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std r11, GPR11(r1) /* Temporary stash */
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mfspr r11, SPRN_PPR
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HMT_MEDIUM
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/* Now get some more GPRS free */
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std r7, GPR7(r1) /* Temporary stash */
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std r12, GPR12(r1) /* '' '' '' */
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ld r12, STACK_PARAM(0)(r1) /* Param 0, thread_struct * */
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std r11, THREAD_TM_PPR(r12) /* Store PPR and free r11 */
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addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */
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/* Make r7 look like an exception frame so that we
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* can use the neat GPRx(n) macros. r7 is NOT a pt_regs ptr!
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*/
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subi r7, r7, STACK_FRAME_OVERHEAD
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/* Sync the userland GPRs 2-12, 14-31 to thread->regs: */
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SAVE_GPR(0, r7) /* user r0 */
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SAVE_GPR(2, r7) /* user r2 */
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SAVE_4GPRS(3, r7) /* user r3-r6 */
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SAVE_GPR(8, r7) /* user r8 */
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SAVE_GPR(9, r7) /* user r9 */
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SAVE_GPR(10, r7) /* user r10 */
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ld r3, PACATMSCRATCH(r13) /* user r1 */
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ld r4, GPR7(r1) /* user r7 */
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ld r5, GPR11(r1) /* user r11 */
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ld r6, GPR12(r1) /* user r12 */
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GET_SCRATCH0(8) /* user r13 */
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std r3, GPR1(r7)
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std r4, GPR7(r7)
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std r5, GPR11(r7)
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std r6, GPR12(r7)
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std r8, GPR13(r7)
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SAVE_NVGPRS(r7) /* user r14-r31 */
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/* ******************** NIP ******************** */
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mfspr r3, SPRN_TFHAR
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std r3, _NIP(r7) /* Returns to failhandler */
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/* The checkpointed NIP is ignored when rescheduling/rechkpting,
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* but is used in signal return to 'wind back' to the abort handler.
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*/
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/* ******************** CR,LR,CCR,MSR ********** */
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mfctr r3
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mflr r4
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mfcr r5
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mfxer r6
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std r3, _CTR(r7)
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std r4, _LINK(r7)
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std r5, _CCR(r7)
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std r6, _XER(r7)
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/* ******************** TAR, DSCR ********** */
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mfspr r3, SPRN_TAR
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mfspr r4, SPRN_DSCR
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std r3, THREAD_TM_TAR(r12)
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std r4, THREAD_TM_DSCR(r12)
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/* MSR and flags: We don't change CRs, and we don't need to alter
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* MSR.
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*/
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/* TM regs, incl TEXASR -- these live in thread_struct. Note they've
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* been updated by the treclaim, to explain to userland the failure
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* cause (aborted).
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*/
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mfspr r0, SPRN_TEXASR
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mfspr r3, SPRN_TFHAR
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mfspr r4, SPRN_TFIAR
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std r0, THREAD_TM_TEXASR(r12)
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std r3, THREAD_TM_TFHAR(r12)
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std r4, THREAD_TM_TFIAR(r12)
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/* AMR is checkpointed too, but is unsupported by Linux. */
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/* Restore original MSR/IRQ state & clear TM mode */
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ld r14, TM_FRAME_L0(r1) /* Orig MSR */
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li r15, 0
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rldimi r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1
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mtmsrd r14
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REST_NVGPRS(r1)
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addi r1, r1, TM_FRAME_SIZE
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ld r4, 8(r1)
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ld r0, 16(r1)
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mtcr r4
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mtlr r0
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ld r2, 40(r1)
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/* Load system default DSCR */
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ld r4, DSCR_DEFAULT@toc(r2)
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ld r0, 0(r4)
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mtspr SPRN_DSCR, r0
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blr
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/* void tm_recheckpoint(struct thread_struct *thread,
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* unsigned long orig_msr)
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* - Restore the checkpointed register state saved by tm_reclaim
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* when we switch_to a process.
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*
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* Call with IRQs off, stacks get all out of sync for
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* some periods in here!
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*/
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_GLOBAL(__tm_recheckpoint)
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mfcr r5
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mflr r0
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std r5, 8(r1)
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std r0, 16(r1)
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std r2, 40(r1)
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stdu r1, -TM_FRAME_SIZE(r1)
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/* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
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* This is used for backing up the NVGPRs:
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*/
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SAVE_NVGPRS(r1)
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std r1, PACAR1(r13)
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/* Load complete register state from ts_ckpt* registers */
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addi r7, r3, PT_CKPT_REGS /* Thread's ckpt_regs */
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/* Make r7 look like an exception frame so that we
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* can use the neat GPRx(n) macros. r7 is now NOT a pt_regs ptr!
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*/
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subi r7, r7, STACK_FRAME_OVERHEAD
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SET_SCRATCH0(r1)
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mfmsr r6
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/* R4 = original MSR to indicate whether thread used FP/Vector etc. */
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/* Enable FP/vec in MSR if necessary! */
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lis r5, MSR_VEC@h
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ori r5, r5, MSR_FP
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and. r5, r4, r5
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beq restore_gprs /* if neither, skip both */
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#ifdef CONFIG_VSX
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BEGIN_FTR_SECTION
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oris r5, r5, MSR_VSX@h
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END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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#endif
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or r5, r6, r5 /* Set MSR.FP+.VSX/.VEC */
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mtmsr r5
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#ifdef CONFIG_ALTIVEC
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/* FP and VEC registers: These are recheckpointed from thread.fpr[]
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* and thread.vr[] respectively. The thread.transact_fpr[] version
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* is more modern, and will be loaded subsequently by any FPUnavailable
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* trap.
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*/
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andis. r0, r4, MSR_VEC@h
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beq dont_restore_vec
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li r5, THREAD_VSCR
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lvx vr0, r3, r5
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mtvscr vr0
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REST_32VRS(0, r5, r3) /* r5 scratch, r3 THREAD ptr */
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ld r5, THREAD_VRSAVE(r3)
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mtspr SPRN_VRSAVE, r5
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#endif
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dont_restore_vec:
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andi. r0, r4, MSR_FP
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beq dont_restore_fp
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lfd fr0, THREAD_FPSCR(r3)
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MTFSF_L(fr0)
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REST_32FPRS_VSRS(0, R4, R3)
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dont_restore_fp:
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mtmsr r6 /* FP/Vec off again! */
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restore_gprs:
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/* ******************** CR,LR,CCR,MSR ********** */
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ld r4, _CTR(r7)
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ld r5, _LINK(r7)
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ld r6, _CCR(r7)
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ld r8, _XER(r7)
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mtctr r4
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mtlr r5
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mtcr r6
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mtxer r8
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/* ******************** TAR ******************** */
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ld r4, THREAD_TM_TAR(r3)
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mtspr SPRN_TAR, r4
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/* Load up the PPR and DSCR in GPRs only at this stage */
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ld r5, THREAD_TM_DSCR(r3)
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ld r6, THREAD_TM_PPR(r3)
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/* MSR and flags: We don't change CRs, and we don't need to alter
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* MSR.
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*/
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REST_4GPRS(0, r7) /* GPR0-3 */
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REST_GPR(4, r7) /* GPR4 */
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REST_4GPRS(8, r7) /* GPR8-11 */
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REST_2GPRS(12, r7) /* GPR12-13 */
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REST_NVGPRS(r7) /* GPR14-31 */
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/* Load up PPR and DSCR here so we don't run with user values for long
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*/
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mtspr SPRN_DSCR, r5
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mtspr SPRN_PPR, r6
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REST_GPR(5, r7) /* GPR5-7 */
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REST_GPR(6, r7)
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ld r7, GPR7(r7)
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/* Commit register state as checkpointed state: */
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TRECHKPT
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HMT_MEDIUM
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/* Our transactional state has now changed.
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*
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* Now just get out of here. Transactional (current) state will be
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* updated once restore is called on the return path in the _switch-ed
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* -to process.
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*/
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GET_PACA(r13)
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GET_SCRATCH0(r1)
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REST_NVGPRS(r1)
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addi r1, r1, TM_FRAME_SIZE
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ld r4, 8(r1)
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ld r0, 16(r1)
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mtcr r4
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mtlr r0
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ld r2, 40(r1)
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|
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/* Load system default DSCR */
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ld r4, DSCR_DEFAULT@toc(r2)
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ld r0, 0(r4)
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mtspr SPRN_DSCR, r0
|
|
|
|
blr
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|
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/* ****************************************************************** */
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