mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-11-01 10:33:27 +00:00
83b83227df
commit 2d49b5987561e480bdbd8692b27fc5f49a1e2f0b upstream.
regcache_sync_block_raw_flush() expects the address of the register after last
register that needs to be synced as its parameter. But the last call to
regcache_sync_block_raw_flush() in regcache_sync_block_raw() passes the address
of the last register in the block. This effectively always skips over the last
register in a block, even if it needs to be synced. In order to fix it increase
the address by one register.
The issue was introduced in commit 75a5f89
("regmap: cache: Write consecutive
registers in a single block write").
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
661 lines
15 KiB
C
661 lines
15 KiB
C
/*
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* Register cache access API
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*
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* Copyright 2011 Wolfson Microelectronics plc
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*
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* Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/device.h>
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#include <trace/events/regmap.h>
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#include <linux/bsearch.h>
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#include <linux/sort.h>
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#include "internal.h"
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static const struct regcache_ops *cache_types[] = {
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®cache_rbtree_ops,
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®cache_lzo_ops,
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®cache_flat_ops,
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};
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static int regcache_hw_init(struct regmap *map)
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{
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int i, j;
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int ret;
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int count;
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unsigned int val;
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void *tmp_buf;
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if (!map->num_reg_defaults_raw)
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return -EINVAL;
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if (!map->reg_defaults_raw) {
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u32 cache_bypass = map->cache_bypass;
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dev_warn(map->dev, "No cache defaults, reading back from HW\n");
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/* Bypass the cache access till data read from HW*/
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map->cache_bypass = 1;
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tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
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if (!tmp_buf)
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return -EINVAL;
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ret = regmap_raw_read(map, 0, tmp_buf,
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map->num_reg_defaults_raw);
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map->cache_bypass = cache_bypass;
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if (ret < 0) {
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kfree(tmp_buf);
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return ret;
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}
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map->reg_defaults_raw = tmp_buf;
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map->cache_free = 1;
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}
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/* calculate the size of reg_defaults */
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for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++) {
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val = regcache_get_val(map, map->reg_defaults_raw, i);
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if (regmap_volatile(map, i * map->reg_stride))
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continue;
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count++;
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}
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map->reg_defaults = kmalloc(count * sizeof(struct reg_default),
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GFP_KERNEL);
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if (!map->reg_defaults) {
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ret = -ENOMEM;
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goto err_free;
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}
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/* fill the reg_defaults */
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map->num_reg_defaults = count;
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for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
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val = regcache_get_val(map, map->reg_defaults_raw, i);
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if (regmap_volatile(map, i * map->reg_stride))
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continue;
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map->reg_defaults[j].reg = i * map->reg_stride;
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map->reg_defaults[j].def = val;
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j++;
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}
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return 0;
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err_free:
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if (map->cache_free)
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kfree(map->reg_defaults_raw);
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return ret;
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}
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int regcache_init(struct regmap *map, const struct regmap_config *config)
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{
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int ret;
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int i;
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void *tmp_buf;
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for (i = 0; i < config->num_reg_defaults; i++)
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if (config->reg_defaults[i].reg % map->reg_stride)
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return -EINVAL;
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if (map->cache_type == REGCACHE_NONE) {
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map->cache_bypass = true;
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return 0;
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}
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for (i = 0; i < ARRAY_SIZE(cache_types); i++)
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if (cache_types[i]->type == map->cache_type)
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break;
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if (i == ARRAY_SIZE(cache_types)) {
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dev_err(map->dev, "Could not match compress type: %d\n",
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map->cache_type);
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return -EINVAL;
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}
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map->num_reg_defaults = config->num_reg_defaults;
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map->num_reg_defaults_raw = config->num_reg_defaults_raw;
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map->reg_defaults_raw = config->reg_defaults_raw;
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map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8);
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map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
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map->cache_present = NULL;
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map->cache_present_nbits = 0;
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map->cache = NULL;
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map->cache_ops = cache_types[i];
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if (!map->cache_ops->read ||
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!map->cache_ops->write ||
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!map->cache_ops->name)
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return -EINVAL;
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/* We still need to ensure that the reg_defaults
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* won't vanish from under us. We'll need to make
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* a copy of it.
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*/
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if (config->reg_defaults) {
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if (!map->num_reg_defaults)
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return -EINVAL;
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tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults *
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sizeof(struct reg_default), GFP_KERNEL);
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if (!tmp_buf)
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return -ENOMEM;
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map->reg_defaults = tmp_buf;
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} else if (map->num_reg_defaults_raw) {
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/* Some devices such as PMICs don't have cache defaults,
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* we cope with this by reading back the HW registers and
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* crafting the cache defaults by hand.
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*/
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ret = regcache_hw_init(map);
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if (ret < 0)
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return ret;
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}
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if (!map->max_register)
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map->max_register = map->num_reg_defaults_raw;
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if (map->cache_ops->init) {
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dev_dbg(map->dev, "Initializing %s cache\n",
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map->cache_ops->name);
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ret = map->cache_ops->init(map);
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if (ret)
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goto err_free;
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}
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return 0;
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err_free:
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kfree(map->reg_defaults);
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if (map->cache_free)
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kfree(map->reg_defaults_raw);
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return ret;
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}
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void regcache_exit(struct regmap *map)
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{
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if (map->cache_type == REGCACHE_NONE)
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return;
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BUG_ON(!map->cache_ops);
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kfree(map->cache_present);
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kfree(map->reg_defaults);
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if (map->cache_free)
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kfree(map->reg_defaults_raw);
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if (map->cache_ops->exit) {
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dev_dbg(map->dev, "Destroying %s cache\n",
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map->cache_ops->name);
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map->cache_ops->exit(map);
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}
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}
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/**
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* regcache_read: Fetch the value of a given register from the cache.
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*
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* @map: map to configure.
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* @reg: The register index.
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* @value: The value to be returned.
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*
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* Return a negative value on failure, 0 on success.
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*/
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int regcache_read(struct regmap *map,
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unsigned int reg, unsigned int *value)
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{
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int ret;
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if (map->cache_type == REGCACHE_NONE)
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return -ENOSYS;
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BUG_ON(!map->cache_ops);
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if (!regmap_volatile(map, reg)) {
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ret = map->cache_ops->read(map, reg, value);
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if (ret == 0)
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trace_regmap_reg_read_cache(map->dev, reg, *value);
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return ret;
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}
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return -EINVAL;
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}
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/**
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* regcache_write: Set the value of a given register in the cache.
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*
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* @map: map to configure.
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* @reg: The register index.
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* @value: The new register value.
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*
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* Return a negative value on failure, 0 on success.
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*/
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int regcache_write(struct regmap *map,
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unsigned int reg, unsigned int value)
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{
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if (map->cache_type == REGCACHE_NONE)
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return 0;
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BUG_ON(!map->cache_ops);
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if (!regmap_writeable(map, reg))
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return -EIO;
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if (!regmap_volatile(map, reg))
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return map->cache_ops->write(map, reg, value);
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return 0;
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}
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/**
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* regcache_sync: Sync the register cache with the hardware.
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*
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* @map: map to configure.
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*
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* Any registers that should not be synced should be marked as
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* volatile. In general drivers can choose not to use the provided
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* syncing functionality if they so require.
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*
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* Return a negative value on failure, 0 on success.
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*/
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int regcache_sync(struct regmap *map)
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{
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int ret = 0;
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unsigned int i;
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const char *name;
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unsigned int bypass;
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BUG_ON(!map->cache_ops || !map->cache_ops->sync);
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map->lock(map->lock_arg);
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/* Remember the initial bypass state */
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bypass = map->cache_bypass;
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dev_dbg(map->dev, "Syncing %s cache\n",
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map->cache_ops->name);
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name = map->cache_ops->name;
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trace_regcache_sync(map->dev, name, "start");
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if (!map->cache_dirty)
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goto out;
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/* Apply any patch first */
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map->cache_bypass = 1;
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for (i = 0; i < map->patch_regs; i++) {
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if (map->patch[i].reg % map->reg_stride) {
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ret = -EINVAL;
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goto out;
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}
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ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
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if (ret != 0) {
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dev_err(map->dev, "Failed to write %x = %x: %d\n",
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map->patch[i].reg, map->patch[i].def, ret);
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goto out;
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}
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}
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map->cache_bypass = 0;
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ret = map->cache_ops->sync(map, 0, map->max_register);
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if (ret == 0)
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map->cache_dirty = false;
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out:
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trace_regcache_sync(map->dev, name, "stop");
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/* Restore the bypass state */
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map->cache_bypass = bypass;
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map->unlock(map->lock_arg);
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return ret;
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}
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EXPORT_SYMBOL_GPL(regcache_sync);
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/**
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* regcache_sync_region: Sync part of the register cache with the hardware.
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*
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* @map: map to sync.
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* @min: first register to sync
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* @max: last register to sync
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*
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* Write all non-default register values in the specified region to
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* the hardware.
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*
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* Return a negative value on failure, 0 on success.
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*/
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int regcache_sync_region(struct regmap *map, unsigned int min,
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unsigned int max)
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{
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int ret = 0;
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const char *name;
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unsigned int bypass;
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BUG_ON(!map->cache_ops || !map->cache_ops->sync);
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map->lock(map->lock_arg);
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/* Remember the initial bypass state */
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bypass = map->cache_bypass;
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name = map->cache_ops->name;
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dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max);
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trace_regcache_sync(map->dev, name, "start region");
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if (!map->cache_dirty)
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goto out;
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ret = map->cache_ops->sync(map, min, max);
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out:
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trace_regcache_sync(map->dev, name, "stop region");
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/* Restore the bypass state */
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map->cache_bypass = bypass;
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map->unlock(map->lock_arg);
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return ret;
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}
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EXPORT_SYMBOL_GPL(regcache_sync_region);
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/**
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* regcache_cache_only: Put a register map into cache only mode
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*
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* @map: map to configure
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* @cache_only: flag if changes should be written to the hardware
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*
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* When a register map is marked as cache only writes to the register
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* map API will only update the register cache, they will not cause
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* any hardware changes. This is useful for allowing portions of
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* drivers to act as though the device were functioning as normal when
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* it is disabled for power saving reasons.
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*/
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void regcache_cache_only(struct regmap *map, bool enable)
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{
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map->lock(map->lock_arg);
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WARN_ON(map->cache_bypass && enable);
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map->cache_only = enable;
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trace_regmap_cache_only(map->dev, enable);
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map->unlock(map->lock_arg);
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}
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EXPORT_SYMBOL_GPL(regcache_cache_only);
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/**
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* regcache_mark_dirty: Mark the register cache as dirty
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*
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* @map: map to mark
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*
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* Mark the register cache as dirty, for example due to the device
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* having been powered down for suspend. If the cache is not marked
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* as dirty then the cache sync will be suppressed.
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*/
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void regcache_mark_dirty(struct regmap *map)
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{
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map->lock(map->lock_arg);
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map->cache_dirty = true;
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map->unlock(map->lock_arg);
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}
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EXPORT_SYMBOL_GPL(regcache_mark_dirty);
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/**
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* regcache_cache_bypass: Put a register map into cache bypass mode
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*
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* @map: map to configure
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* @cache_bypass: flag if changes should not be written to the hardware
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*
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* When a register map is marked with the cache bypass option, writes
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* to the register map API will only update the hardware and not the
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* the cache directly. This is useful when syncing the cache back to
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* the hardware.
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*/
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void regcache_cache_bypass(struct regmap *map, bool enable)
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{
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map->lock(map->lock_arg);
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WARN_ON(map->cache_only && enable);
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map->cache_bypass = enable;
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trace_regmap_cache_bypass(map->dev, enable);
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map->unlock(map->lock_arg);
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}
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EXPORT_SYMBOL_GPL(regcache_cache_bypass);
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int regcache_set_reg_present(struct regmap *map, unsigned int reg)
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{
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unsigned long *cache_present;
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unsigned int cache_present_size;
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unsigned int nregs;
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int i;
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nregs = reg + 1;
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cache_present_size = BITS_TO_LONGS(nregs);
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cache_present_size *= sizeof(long);
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if (!map->cache_present) {
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cache_present = kmalloc(cache_present_size, GFP_KERNEL);
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if (!cache_present)
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return -ENOMEM;
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bitmap_zero(cache_present, nregs);
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map->cache_present = cache_present;
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map->cache_present_nbits = nregs;
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}
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if (nregs > map->cache_present_nbits) {
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cache_present = krealloc(map->cache_present,
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cache_present_size, GFP_KERNEL);
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if (!cache_present)
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return -ENOMEM;
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for (i = 0; i < nregs; i++)
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if (i >= map->cache_present_nbits)
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clear_bit(i, cache_present);
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map->cache_present = cache_present;
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map->cache_present_nbits = nregs;
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}
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set_bit(reg, map->cache_present);
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return 0;
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}
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bool regcache_set_val(struct regmap *map, void *base, unsigned int idx,
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unsigned int val)
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{
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if (regcache_get_val(map, base, idx) == val)
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return true;
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/* Use device native format if possible */
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if (map->format.format_val) {
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map->format.format_val(base + (map->cache_word_size * idx),
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val, 0);
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return false;
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}
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switch (map->cache_word_size) {
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case 1: {
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u8 *cache = base;
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cache[idx] = val;
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break;
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}
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case 2: {
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u16 *cache = base;
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cache[idx] = val;
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break;
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}
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case 4: {
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u32 *cache = base;
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cache[idx] = val;
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break;
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}
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default:
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BUG();
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}
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return false;
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}
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unsigned int regcache_get_val(struct regmap *map, const void *base,
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unsigned int idx)
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{
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if (!base)
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return -EINVAL;
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/* Use device native format if possible */
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if (map->format.parse_val)
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return map->format.parse_val(regcache_get_val_addr(map, base,
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idx));
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switch (map->cache_word_size) {
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case 1: {
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const u8 *cache = base;
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return cache[idx];
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}
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case 2: {
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const u16 *cache = base;
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return cache[idx];
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}
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case 4: {
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const u32 *cache = base;
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return cache[idx];
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}
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default:
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BUG();
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}
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/* unreachable */
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return -1;
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}
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static int regcache_default_cmp(const void *a, const void *b)
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{
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const struct reg_default *_a = a;
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const struct reg_default *_b = b;
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return _a->reg - _b->reg;
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}
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int regcache_lookup_reg(struct regmap *map, unsigned int reg)
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{
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struct reg_default key;
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struct reg_default *r;
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|
|
key.reg = reg;
|
|
key.def = 0;
|
|
|
|
r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,
|
|
sizeof(struct reg_default), regcache_default_cmp);
|
|
|
|
if (r)
|
|
return r - map->reg_defaults;
|
|
else
|
|
return -ENOENT;
|
|
}
|
|
|
|
static int regcache_sync_block_single(struct regmap *map, void *block,
|
|
unsigned int block_base,
|
|
unsigned int start, unsigned int end)
|
|
{
|
|
unsigned int i, regtmp, val;
|
|
int ret;
|
|
|
|
for (i = start; i < end; i++) {
|
|
regtmp = block_base + (i * map->reg_stride);
|
|
|
|
if (!regcache_reg_present(map, regtmp))
|
|
continue;
|
|
|
|
val = regcache_get_val(map, block, i);
|
|
|
|
/* Is this the hardware default? If so skip. */
|
|
ret = regcache_lookup_reg(map, regtmp);
|
|
if (ret >= 0 && val == map->reg_defaults[ret].def)
|
|
continue;
|
|
|
|
map->cache_bypass = 1;
|
|
|
|
ret = _regmap_write(map, regtmp, val);
|
|
|
|
map->cache_bypass = 0;
|
|
if (ret != 0)
|
|
return ret;
|
|
dev_dbg(map->dev, "Synced register %#x, value %#x\n",
|
|
regtmp, val);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
|
|
unsigned int base, unsigned int cur)
|
|
{
|
|
size_t val_bytes = map->format.val_bytes;
|
|
int ret, count;
|
|
|
|
if (*data == NULL)
|
|
return 0;
|
|
|
|
count = cur - base;
|
|
|
|
dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
|
|
count * val_bytes, count, base, cur - 1);
|
|
|
|
map->cache_bypass = 1;
|
|
|
|
ret = _regmap_raw_write(map, base, *data, count * val_bytes,
|
|
false);
|
|
|
|
map->cache_bypass = 0;
|
|
|
|
*data = NULL;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int regcache_sync_block_raw(struct regmap *map, void *block,
|
|
unsigned int block_base, unsigned int start,
|
|
unsigned int end)
|
|
{
|
|
unsigned int i, val;
|
|
unsigned int regtmp = 0;
|
|
unsigned int base = 0;
|
|
const void *data = NULL;
|
|
int ret;
|
|
|
|
for (i = start; i < end; i++) {
|
|
regtmp = block_base + (i * map->reg_stride);
|
|
|
|
if (!regcache_reg_present(map, regtmp)) {
|
|
ret = regcache_sync_block_raw_flush(map, &data,
|
|
base, regtmp);
|
|
if (ret != 0)
|
|
return ret;
|
|
continue;
|
|
}
|
|
|
|
val = regcache_get_val(map, block, i);
|
|
|
|
/* Is this the hardware default? If so skip. */
|
|
ret = regcache_lookup_reg(map, regtmp);
|
|
if (ret >= 0 && val == map->reg_defaults[ret].def) {
|
|
ret = regcache_sync_block_raw_flush(map, &data,
|
|
base, regtmp);
|
|
if (ret != 0)
|
|
return ret;
|
|
continue;
|
|
}
|
|
|
|
if (!data) {
|
|
data = regcache_get_val_addr(map, block, i);
|
|
base = regtmp;
|
|
}
|
|
}
|
|
|
|
return regcache_sync_block_raw_flush(map, &data, base, regtmp +
|
|
map->reg_stride);
|
|
}
|
|
|
|
int regcache_sync_block(struct regmap *map, void *block,
|
|
unsigned int block_base, unsigned int start,
|
|
unsigned int end)
|
|
{
|
|
if (regmap_can_raw_write(map))
|
|
return regcache_sync_block_raw(map, block, block_base,
|
|
start, end);
|
|
else
|
|
return regcache_sync_block_single(map, block, block_base,
|
|
start, end);
|
|
}
|