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https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
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32351a28a7
This adds preliminary support for the SH7785-based Highlander board. Some of the Highlander support code is reordered so that most of it can be reused directly. This also plugs in missing SH7785 checks in the places that need it, as this is the first board to support the CPU. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
248 lines
6 KiB
C
248 lines
6 KiB
C
/*
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* arch/sh/kernel/cpu/sh4/probe.c
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*
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* CPU Subtype Probing for SH-4.
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*
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* Copyright (C) 2001 - 2006 Paul Mundt
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* Copyright (C) 2003 Richard Curnow
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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int __init detect_cpu_and_cache_system(void)
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{
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unsigned long pvr, prr, cvr;
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unsigned long size;
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static unsigned long sizes[16] = {
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[1] = (1 << 12),
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[2] = (1 << 13),
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[4] = (1 << 14),
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[8] = (1 << 15),
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[9] = (1 << 16)
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};
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pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffffff;
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prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
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cvr = (ctrl_inl(CCN_CVR));
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/*
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* Setup some sane SH-4 defaults for the icache
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*/
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current_cpu_data.icache.way_incr = (1 << 13);
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current_cpu_data.icache.entry_shift = 5;
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current_cpu_data.icache.sets = 256;
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current_cpu_data.icache.ways = 1;
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current_cpu_data.icache.linesz = L1_CACHE_BYTES;
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/*
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* And again for the dcache ..
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*/
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current_cpu_data.dcache.way_incr = (1 << 14);
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current_cpu_data.dcache.entry_shift = 5;
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current_cpu_data.dcache.sets = 512;
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current_cpu_data.dcache.ways = 1;
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current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
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/*
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* Setup some generic flags we can probe
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* (L2 and DSP detection only work on SH-4A)
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*/
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if (((pvr >> 16) & 0xff) == 0x10) {
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if ((cvr & 0x02000000) == 0)
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current_cpu_data.flags |= CPU_HAS_L2_CACHE;
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if ((cvr & 0x10000000) == 0)
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current_cpu_data.flags |= CPU_HAS_DSP;
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current_cpu_data.flags |= CPU_HAS_LLSC;
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}
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/* FPU detection works for everyone */
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if ((cvr & 0x20000000) == 1)
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current_cpu_data.flags |= CPU_HAS_FPU;
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/* Mask off the upper chip ID */
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pvr &= 0xffff;
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/*
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* Probe the underlying processor version/revision and
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* adjust cpu_data setup accordingly.
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*/
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switch (pvr) {
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case 0x205:
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current_cpu_data.type = CPU_SH7750;
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current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
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CPU_HAS_PERF_COUNTER;
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break;
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case 0x206:
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current_cpu_data.type = CPU_SH7750S;
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current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
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CPU_HAS_PERF_COUNTER;
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break;
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case 0x1100:
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current_cpu_data.type = CPU_SH7751;
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current_cpu_data.flags |= CPU_HAS_FPU;
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break;
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case 0x2000:
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current_cpu_data.type = CPU_SH73180;
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current_cpu_data.icache.ways = 4;
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current_cpu_data.dcache.ways = 4;
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current_cpu_data.flags |= CPU_HAS_LLSC;
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break;
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case 0x2001:
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case 0x2004:
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current_cpu_data.type = CPU_SH7770;
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current_cpu_data.icache.ways = 4;
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current_cpu_data.dcache.ways = 4;
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current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
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break;
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case 0x2006:
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case 0x200A:
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if (prr == 0x61)
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current_cpu_data.type = CPU_SH7781;
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else
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current_cpu_data.type = CPU_SH7780;
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current_cpu_data.icache.ways = 4;
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current_cpu_data.dcache.ways = 4;
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current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
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CPU_HAS_LLSC;
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break;
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case 0x3000:
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case 0x3003:
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case 0x3009:
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current_cpu_data.type = CPU_SH7343;
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current_cpu_data.icache.ways = 4;
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current_cpu_data.dcache.ways = 4;
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current_cpu_data.flags |= CPU_HAS_LLSC;
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break;
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case 0x3004:
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case 0x3007:
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current_cpu_data.type = CPU_SH7785;
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current_cpu_data.icache.ways = 4;
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current_cpu_data.dcache.ways = 4;
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current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
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CPU_HAS_LLSC;
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break;
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case 0x3008:
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if (prr == 0xa0) {
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current_cpu_data.type = CPU_SH7722;
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current_cpu_data.icache.ways = 4;
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current_cpu_data.dcache.ways = 4;
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current_cpu_data.flags |= CPU_HAS_LLSC;
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}
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break;
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case 0x8000:
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current_cpu_data.type = CPU_ST40RA;
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current_cpu_data.flags |= CPU_HAS_FPU;
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break;
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case 0x8100:
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current_cpu_data.type = CPU_ST40GX1;
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current_cpu_data.flags |= CPU_HAS_FPU;
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break;
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case 0x700:
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current_cpu_data.type = CPU_SH4_501;
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current_cpu_data.icache.ways = 2;
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current_cpu_data.dcache.ways = 2;
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break;
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case 0x600:
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current_cpu_data.type = CPU_SH4_202;
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current_cpu_data.icache.ways = 2;
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current_cpu_data.dcache.ways = 2;
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current_cpu_data.flags |= CPU_HAS_FPU;
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break;
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case 0x500 ... 0x501:
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switch (prr) {
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case 0x10:
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current_cpu_data.type = CPU_SH7750R;
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break;
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case 0x11:
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current_cpu_data.type = CPU_SH7751R;
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break;
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case 0x50 ... 0x5f:
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current_cpu_data.type = CPU_SH7760;
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break;
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}
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current_cpu_data.icache.ways = 2;
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current_cpu_data.dcache.ways = 2;
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current_cpu_data.flags |= CPU_HAS_FPU;
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break;
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default:
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current_cpu_data.type = CPU_SH_NONE;
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break;
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}
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#ifdef CONFIG_SH_DIRECT_MAPPED
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current_cpu_data.icache.ways = 1;
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current_cpu_data.dcache.ways = 1;
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#endif
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#ifdef CONFIG_CPU_HAS_PTEA
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current_cpu_data.flags |= CPU_HAS_PTEA;
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#endif
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/*
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* On anything that's not a direct-mapped cache, look to the CVR
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* for I/D-cache specifics.
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*/
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if (current_cpu_data.icache.ways > 1) {
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size = sizes[(cvr >> 20) & 0xf];
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current_cpu_data.icache.way_incr = (size >> 1);
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current_cpu_data.icache.sets = (size >> 6);
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}
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/* And the rest of the D-cache */
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if (current_cpu_data.dcache.ways > 1) {
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size = sizes[(cvr >> 16) & 0xf];
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current_cpu_data.dcache.way_incr = (size >> 1);
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current_cpu_data.dcache.sets = (size >> 6);
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}
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/*
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* Setup the L2 cache desc
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*
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* SH-4A's have an optional PIPT L2.
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*/
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if (current_cpu_data.flags & CPU_HAS_L2_CACHE) {
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/*
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* Size calculation is much more sensible
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* than it is for the L1.
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*
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* Sizes are 128KB, 258KB, 512KB, and 1MB.
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*/
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size = (cvr & 0xf) << 17;
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BUG_ON(!size);
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current_cpu_data.scache.way_incr = (1 << 16);
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current_cpu_data.scache.entry_shift = 5;
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current_cpu_data.scache.ways = 4;
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current_cpu_data.scache.linesz = L1_CACHE_BYTES;
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current_cpu_data.scache.entry_mask =
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(current_cpu_data.scache.way_incr -
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current_cpu_data.scache.linesz);
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current_cpu_data.scache.sets = size /
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(current_cpu_data.scache.linesz *
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current_cpu_data.scache.ways);
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current_cpu_data.scache.way_size =
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(current_cpu_data.scache.sets *
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current_cpu_data.scache.linesz);
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}
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return 0;
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}
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