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34db3c078a
commit f0a56c480196a98479760862468cc95879df3de0 upstream. It can happen that configurations are running in a single-channel mode even with a dual-channel memory controller, by, say, putting the DIMMs only on the one channel and leaving the other empty. This causes a problem in init_csrows which implicitly assumes that when the second channel is enabled, i.e. channel 1, the struct dimm hierarchy will be present. Which is not. So always allocate two channels unconditionally. This provides for the nice side effect that the data structures are initialized so some day, when memory hotplug is supported, it should just work out of the box when all of a sudden a second channel appears. Reported-and-tested-by: Roger Leigh <rleigh@debian.org> Signed-off-by: Borislav Petkov <bp@suse.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
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.. | ||
amd64_edac.c | ||
amd64_edac.h | ||
amd64_edac_dbg.c | ||
amd64_edac_inj.c | ||
amd76x_edac.c | ||
amd8111_edac.c | ||
amd8111_edac.h | ||
amd8131_edac.c | ||
amd8131_edac.h | ||
cell_edac.c | ||
cpc925_edac.c | ||
e7xxx_edac.c | ||
e752x_edac.c | ||
edac_core.h | ||
edac_device.c | ||
edac_device_sysfs.c | ||
edac_mc.c | ||
edac_mc_sysfs.c | ||
edac_module.c | ||
edac_module.h | ||
edac_pci.c | ||
edac_pci_sysfs.c | ||
edac_stub.c | ||
ghes_edac.c | ||
highbank_l2_edac.c | ||
highbank_mc_edac.c | ||
i7core_edac.c | ||
i3000_edac.c | ||
i3200_edac.c | ||
i5000_edac.c | ||
i5100_edac.c | ||
i5400_edac.c | ||
i7300_edac.c | ||
i82443bxgx_edac.c | ||
i82860_edac.c | ||
i82875p_edac.c | ||
i82975x_edac.c | ||
Kconfig | ||
Makefile | ||
mce_amd.c | ||
mce_amd.h | ||
mce_amd_inj.c | ||
mpc85xx_edac.c | ||
mpc85xx_edac.h | ||
mv64x60_edac.c | ||
mv64x60_edac.h | ||
octeon_edac-l2c.c | ||
octeon_edac-lmc.c | ||
octeon_edac-pc.c | ||
octeon_edac-pci.c | ||
pasemi_edac.c | ||
ppc4xx_edac.c | ||
ppc4xx_edac.h | ||
r82600_edac.c | ||
sb_edac.c | ||
tile_edac.c | ||
x38_edac.c |