mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-11-01 10:33:27 +00:00
867e359b97
This change is the core kernel support for TILEPro and TILE64 chips. No driver support (except the console driver) is included yet. This includes the relevant Linux headers in asm/; the low-level low-level "Tile architecture" headers in arch/, which are shared with the hypervisor, etc., and are build-system agnostic; and the relevant hypervisor headers in hv/. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Reviewed-by: Paul Mundt <lethal@linux-sh.org>
280 lines
6.4 KiB
ArmAsm
280 lines
6.4 KiB
ArmAsm
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*
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* copy new kernel into place and then call hv_reexec
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*
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*/
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#include <linux/linkage.h>
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#include <arch/chip.h>
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#include <asm/page.h>
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#include <hv/hypervisor.h>
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#define ___hvb MEM_SV_INTRPT + HV_GLUE_START_CPA
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#define ___hv_dispatch(f) (___hvb + (HV_DISPATCH_ENTRY_SIZE * f))
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#define ___hv_console_putc ___hv_dispatch(HV_DISPATCH_CONSOLE_PUTC)
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#define ___hv_halt ___hv_dispatch(HV_DISPATCH_HALT)
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#define ___hv_reexec ___hv_dispatch(HV_DISPATCH_REEXEC)
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#define ___hv_flush_remote ___hv_dispatch(HV_DISPATCH_FLUSH_REMOTE)
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#undef RELOCATE_NEW_KERNEL_VERBOSE
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STD_ENTRY(relocate_new_kernel)
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move r30, r0 /* page list */
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move r31, r1 /* address of page we are on */
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move r32, r2 /* start address of new kernel */
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shri r1, r1, PAGE_SHIFT
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addi r1, r1, 1
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shli sp, r1, PAGE_SHIFT
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addi sp, sp, -8
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/* we now have a stack (whether we need one or not) */
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moveli r40, lo16(___hv_console_putc)
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auli r40, r40, ha16(___hv_console_putc)
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#ifdef RELOCATE_NEW_KERNEL_VERBOSE
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moveli r0, 'r'
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jalr r40
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moveli r0, '_'
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jalr r40
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moveli r0, 'n'
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jalr r40
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moveli r0, '_'
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jalr r40
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moveli r0, 'k'
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jalr r40
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moveli r0, '\n'
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jalr r40
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#endif
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/*
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* Throughout this code r30 is pointer to the element of page
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* list we are working on.
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*
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* Normally we get to the next element of the page list by
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* incrementing r30 by four. The exception is if the element
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* on the page list is an IND_INDIRECTION in which case we use
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* the element with the low bits masked off as the new value
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* of r30.
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*
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* To get this started, we need the value passed to us (which
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* will always be an IND_INDIRECTION) in memory somewhere with
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* r30 pointing at it. To do that, we push the value passed
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* to us on the stack and make r30 point to it.
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*/
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sw sp, r30
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move r30, sp
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addi sp, sp, -8
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#if CHIP_HAS_CBOX_HOME_MAP()
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/*
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* On TILEPro, we need to flush all tiles' caches, since we may
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* have been doing hash-for-home caching there. Note that we
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* must do this _after_ we're completely done modifying any memory
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* other than our output buffer (which we know is locally cached).
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* We want the caches to be fully clean when we do the reexec,
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* because the hypervisor is going to do this flush again at that
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* point, and we don't want that second flush to overwrite any memory.
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*/
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{
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move r0, zero /* cache_pa */
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move r1, zero
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}
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{
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auli r2, zero, ha16(HV_FLUSH_EVICT_L2) /* cache_control */
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movei r3, -1 /* cache_cpumask; -1 means all client tiles */
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}
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{
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move r4, zero /* tlb_va */
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move r5, zero /* tlb_length */
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}
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{
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move r6, zero /* tlb_pgsize */
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move r7, zero /* tlb_cpumask */
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}
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{
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move r8, zero /* asids */
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moveli r20, lo16(___hv_flush_remote)
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}
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{
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move r9, zero /* asidcount */
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auli r20, r20, ha16(___hv_flush_remote)
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}
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jalr r20
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#endif
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/* r33 is destination pointer, default to zero */
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moveli r33, 0
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.Lloop: lw r10, r30
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andi r9, r10, 0xf /* low 4 bits tell us what type it is */
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xor r10, r10, r9 /* r10 is now value with low 4 bits stripped */
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seqi r0, r9, 0x1 /* IND_DESTINATION */
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bzt r0, .Ltry2
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move r33, r10
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#ifdef RELOCATE_NEW_KERNEL_VERBOSE
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moveli r0, 'd'
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jalr r40
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#endif
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addi r30, r30, 4
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j .Lloop
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.Ltry2:
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seqi r0, r9, 0x2 /* IND_INDIRECTION */
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bzt r0, .Ltry4
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move r30, r10
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#ifdef RELOCATE_NEW_KERNEL_VERBOSE
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moveli r0, 'i'
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jalr r40
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#endif
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j .Lloop
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.Ltry4:
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seqi r0, r9, 0x4 /* IND_DONE */
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bzt r0, .Ltry8
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mf
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#ifdef RELOCATE_NEW_KERNEL_VERBOSE
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moveli r0, 'D'
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jalr r40
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moveli r0, '\n'
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jalr r40
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#endif
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move r0, r32
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moveli r1, 0 /* arg to hv_reexec is 64 bits */
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moveli r41, lo16(___hv_reexec)
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auli r41, r41, ha16(___hv_reexec)
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jalr r41
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/* we should not get here */
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moveli r0, '?'
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jalr r40
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moveli r0, '\n'
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jalr r40
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j .Lhalt
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.Ltry8: seqi r0, r9, 0x8 /* IND_SOURCE */
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bz r0, .Lerr /* unknown type */
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/* copy page at r10 to page at r33 */
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move r11, r33
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moveli r0, lo16(PAGE_SIZE)
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auli r0, r0, ha16(PAGE_SIZE)
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add r33, r33, r0
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/* copy word at r10 to word at r11 until r11 equals r33 */
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/* We know page size must be multiple of 16, so we can unroll
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* 16 times safely without any edge case checking.
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*
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* Issue a flush of the destination every 16 words to avoid
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* incoherence when starting the new kernel. (Now this is
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* just good paranoia because the hv_reexec call will also
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* take care of this.)
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*/
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1:
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{ lw r0, r10; addi r10, r10, 4 }
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{ sw r11, r0; addi r11, r11, 4 }
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{ lw r0, r10; addi r10, r10, 4 }
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{ sw r11, r0; addi r11, r11, 4 }
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{ lw r0, r10; addi r10, r10, 4 }
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{ sw r11, r0; addi r11, r11, 4 }
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{ lw r0, r10; addi r10, r10, 4 }
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{ sw r11, r0; addi r11, r11, 4 }
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{ lw r0, r10; addi r10, r10, 4 }
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{ sw r11, r0; addi r11, r11, 4 }
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{ lw r0, r10; addi r10, r10, 4 }
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{ sw r11, r0; addi r11, r11, 4 }
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{ lw r0, r10; addi r10, r10, 4 }
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{ sw r11, r0; addi r11, r11, 4 }
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{ lw r0, r10; addi r10, r10, 4 }
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{ sw r11, r0; addi r11, r11, 4 }
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{ lw r0, r10; addi r10, r10, 4 }
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{ sw r11, r0; addi r11, r11, 4 }
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{ lw r0, r10; addi r10, r10, 4 }
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{ sw r11, r0; addi r11, r11, 4 }
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{ lw r0, r10; addi r10, r10, 4 }
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{ sw r11, r0; addi r11, r11, 4 }
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{ lw r0, r10; addi r10, r10, 4 }
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{ sw r11, r0; addi r11, r11, 4 }
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{ lw r0, r10; addi r10, r10, 4 }
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{ sw r11, r0; addi r11, r11, 4 }
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{ lw r0, r10; addi r10, r10, 4 }
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{ sw r11, r0; addi r11, r11, 4 }
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{ lw r0, r10; addi r10, r10, 4 }
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{ sw r11, r0; addi r11, r11, 4 }
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{ lw r0, r10; addi r10, r10, 4 }
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{ sw r11, r0 }
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{ flush r11 ; addi r11, r11, 4 }
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seq r0, r33, r11
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bzt r0, 1b
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#ifdef RELOCATE_NEW_KERNEL_VERBOSE
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moveli r0, 's'
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jalr r40
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#endif
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addi r30, r30, 4
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j .Lloop
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.Lerr: moveli r0, 'e'
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jalr r40
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moveli r0, 'r'
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jalr r40
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moveli r0, 'r'
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jalr r40
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moveli r0, '\n'
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jalr r40
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.Lhalt:
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moveli r41, lo16(___hv_halt)
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auli r41, r41, ha16(___hv_halt)
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jalr r41
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STD_ENDPROC(relocate_new_kernel)
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.section .rodata,"a"
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.globl relocate_new_kernel_size
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relocate_new_kernel_size:
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.long .Lend_relocate_new_kernel - relocate_new_kernel
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