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https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
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0637a70a5d
Some buggy systems can machine check when config space accesses happen for some non existent devices. i386/x86-64 do some early device scans that might trigger this. Allow pci=noearly to disable this. Also when type 1 is disabling also don't do any early accesses which are always type1. This moves the pci= configuration parsing to be a early parameter. I don't think this can break anything because it only changes a single global that is only used by PCI. Cc: gregkh@suse.de Cc: Trammell Hudson <hudson@osresearch.net> Signed-off-by: Andi Kleen <ak@suse.de>
80 lines
1.8 KiB
C
80 lines
1.8 KiB
C
/*
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* Do early PCI probing for bug detection when the main PCI subsystem is
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* not up yet.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/acpi.h>
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#include <asm/pci-direct.h>
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#include <asm/acpi.h>
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#include <asm/apic.h>
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#ifdef CONFIG_ACPI
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static int nvidia_hpet_detected __initdata;
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static int __init nvidia_hpet_check(unsigned long phys, unsigned long size)
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{
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nvidia_hpet_detected = 1;
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return 0;
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}
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#endif
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static int __init check_bridge(int vendor, int device)
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{
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#ifdef CONFIG_ACPI
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/* According to Nvidia all timer overrides are bogus unless HPET
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is enabled. */
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if (vendor == PCI_VENDOR_ID_NVIDIA) {
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nvidia_hpet_detected = 0;
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acpi_table_parse(ACPI_HPET, nvidia_hpet_check);
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if (nvidia_hpet_detected == 0) {
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acpi_skip_timer_override = 1;
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}
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}
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#endif
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if (vendor == PCI_VENDOR_ID_ATI && timer_over_8254 == 1) {
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timer_over_8254 = 0;
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printk(KERN_INFO "ATI board detected. Disabling timer routing "
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"over 8254.\n");
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}
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return 0;
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}
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void __init check_acpi_pci(void)
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{
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int num, slot, func;
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/* Assume the machine supports type 1. If not it will
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always read ffffffff and should not have any side effect.
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Actually a few buggy systems can machine check. Allow the user
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to disable it by command line option at least -AK */
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if (!early_pci_allowed())
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return;
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/* Poor man's PCI discovery */
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for (num = 0; num < 32; num++) {
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for (slot = 0; slot < 32; slot++) {
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for (func = 0; func < 8; func++) {
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u32 class;
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u32 vendor;
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class = read_pci_config(num, slot, func,
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PCI_CLASS_REVISION);
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if (class == 0xffffffff)
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break;
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if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
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continue;
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vendor = read_pci_config(num, slot, func,
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PCI_VENDOR_ID);
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if (check_bridge(vendor & 0xffff, vendor >> 16))
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return;
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}
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}
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}
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}
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