98 lines
3.7 KiB
C
98 lines
3.7 KiB
C
/*
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* Copyright (C) 2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_ESR_H
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#define __ASM_ESR_H
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#define ESR_EL1_WRITE (1 << 6)
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#define ESR_EL1_CM (1 << 8)
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#define ESR_EL1_IL (1 << 25)
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#define ESR_EL1_EC_SHIFT (26)
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#define ESR_EL1_EC_UNKNOWN (0x00)
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#define ESR_EL1_EC_WFI (0x01)
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#define ESR_EL1_EC_CP15_32 (0x03)
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#define ESR_EL1_EC_CP15_64 (0x04)
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#define ESR_EL1_EC_CP14_MR (0x05)
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#define ESR_EL1_EC_CP14_LS (0x06)
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#define ESR_EL1_EC_FP_ASIMD (0x07)
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#define ESR_EL1_EC_CP10_ID (0x08)
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#define ESR_EL1_EC_CP14_64 (0x0C)
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#define ESR_EL1_EC_ILL_ISS (0x0E)
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#define ESR_EL1_EC_SVC32 (0x11)
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#define ESR_EL1_EC_SVC64 (0x15)
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#define ESR_EL1_EC_SYS64 (0x18)
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#define ESR_EL1_EC_IABT_EL0 (0x20)
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#define ESR_EL1_EC_IABT_EL1 (0x21)
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#define ESR_EL1_EC_PC_ALIGN (0x22)
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#define ESR_EL1_EC_DABT_EL0 (0x24)
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#define ESR_EL1_EC_DABT_EL1 (0x25)
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#define ESR_EL1_EC_SP_ALIGN (0x26)
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#define ESR_EL1_EC_FP_EXC32 (0x28)
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#define ESR_EL1_EC_FP_EXC64 (0x2C)
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#define ESR_EL1_EC_SERROR (0x2F)
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#define ESR_EL1_EC_BREAKPT_EL0 (0x30)
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#define ESR_EL1_EC_BREAKPT_EL1 (0x31)
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#define ESR_EL1_EC_SOFTSTP_EL0 (0x32)
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#define ESR_EL1_EC_SOFTSTP_EL1 (0x33)
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#define ESR_EL1_EC_WATCHPT_EL0 (0x34)
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#define ESR_EL1_EC_WATCHPT_EL1 (0x35)
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#define ESR_EL1_EC_BKPT32 (0x38)
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#define ESR_EL1_EC_BRK64 (0x3C)
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/* ISS field definitions for System instruction traps */
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#define ESR_ELx_SYS64_ISS_RES0_SHIFT 22
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#define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
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#define ESR_ELx_SYS64_ISS_DIR_MASK 0x1
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#define ESR_ELx_SYS64_ISS_DIR_READ 0x1
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#define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0
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#define ESR_ELx_SYS64_ISS_RT_SHIFT 5
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#define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
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#define ESR_ELx_SYS64_ISS_CRM_SHIFT 1
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#define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
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#define ESR_ELx_SYS64_ISS_CRN_SHIFT 10
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#define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
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#define ESR_ELx_SYS64_ISS_OP1_SHIFT 14
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#define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
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#define ESR_ELx_SYS64_ISS_OP2_SHIFT 17
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#define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
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#define ESR_ELx_SYS64_ISS_OP0_SHIFT 20
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#define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
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#define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
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ESR_ELx_SYS64_ISS_OP1_MASK | \
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ESR_ELx_SYS64_ISS_OP2_MASK | \
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ESR_ELx_SYS64_ISS_CRN_MASK | \
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ESR_ELx_SYS64_ISS_CRM_MASK)
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#define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \
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(((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \
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((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \
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((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
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((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \
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((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
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#define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \
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ESR_ELx_SYS64_ISS_DIR_MASK)
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#define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
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ESR_ELx_SYS64_ISS_DIR_READ)
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#define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \
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ESR_ELx_SYS64_ISS_DIR_READ)
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#endif /* __ASM_ESR_H */
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