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119fd635e3
During the introduction of the Allwinner SoC platforms, sunxi was initially meant as a generic name for all the variants of the Allwinner SoC. It was ok at the time of the support of only the A10 and A13 that looks pretty much the same, but it's beginning to be troublesome with the future addition of the Allwinner A31 (sun6i) that is quite different, and would introduce some weird logic, where sunxi would actually mean in some case sun4i and sun5i but without sun6i... Moreover, it makes the compatible strings naming scheme not consistent with other architectures, where usually for this kind of compability, we just use the oldest SoC name that has this IP, so let's do just this. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
148 lines
3.8 KiB
C
148 lines
3.8 KiB
C
/*
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* Allwinner A1X SoCs timer handling.
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*
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* Copyright (C) 2012 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* Based on code from
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Benn Huang <benn@allwinnertech.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqreturn.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#define TIMER_IRQ_EN_REG 0x00
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#define TIMER_IRQ_EN(val) (1 << val)
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#define TIMER_IRQ_ST_REG 0x04
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#define TIMER_CTL_REG(val) (0x10 * val + 0x10)
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#define TIMER_CTL_ENABLE (1 << 0)
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#define TIMER_CTL_AUTORELOAD (1 << 1)
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#define TIMER_CTL_ONESHOT (1 << 7)
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#define TIMER_INTVAL_REG(val) (0x10 * val + 0x14)
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#define TIMER_CNTVAL_REG(val) (0x10 * val + 0x18)
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#define TIMER_SCAL 16
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static void __iomem *timer_base;
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static void sun4i_clkevt_mode(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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u32 u = readl(timer_base + TIMER_CTL_REG(0));
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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u &= ~(TIMER_CTL_ONESHOT);
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writel(u | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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writel(u | TIMER_CTL_ONESHOT, timer_base + TIMER_CTL_REG(0));
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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writel(u & ~(TIMER_CTL_ENABLE), timer_base + TIMER_CTL_REG(0));
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break;
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}
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}
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static int sun4i_clkevt_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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u32 u = readl(timer_base + TIMER_CTL_REG(0));
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writel(evt, timer_base + TIMER_CNTVAL_REG(0));
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writel(u | TIMER_CTL_ENABLE | TIMER_CTL_AUTORELOAD,
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timer_base + TIMER_CTL_REG(0));
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return 0;
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}
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static struct clock_event_device sun4i_clockevent = {
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.name = "sun4i_tick",
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.rating = 300,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = sun4i_clkevt_mode,
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.set_next_event = sun4i_clkevt_next_event,
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};
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static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = (struct clock_event_device *)dev_id;
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writel(0x1, timer_base + TIMER_IRQ_ST_REG);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction sun4i_timer_irq = {
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.name = "sun4i_timer0",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = sun4i_timer_interrupt,
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.dev_id = &sun4i_clockevent,
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};
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static void __init sun4i_timer_init(struct device_node *node)
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{
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unsigned long rate = 0;
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struct clk *clk;
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int ret, irq;
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u32 val;
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timer_base = of_iomap(node, 0);
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if (!timer_base)
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panic("Can't map registers");
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irq = irq_of_parse_and_map(node, 0);
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if (irq <= 0)
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panic("Can't parse IRQ");
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk))
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panic("Can't get timer clock");
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rate = clk_get_rate(clk);
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writel(rate / (TIMER_SCAL * HZ),
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timer_base + TIMER_INTVAL_REG(0));
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/* set clock source to HOSC, 16 pre-division */
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val = readl(timer_base + TIMER_CTL_REG(0));
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val &= ~(0x07 << 4);
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val &= ~(0x03 << 2);
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val |= (4 << 4) | (1 << 2);
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writel(val, timer_base + TIMER_CTL_REG(0));
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/* set mode to auto reload */
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val = readl(timer_base + TIMER_CTL_REG(0));
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writel(val | TIMER_CTL_AUTORELOAD, timer_base + TIMER_CTL_REG(0));
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ret = setup_irq(irq, &sun4i_timer_irq);
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if (ret)
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pr_warn("failed to setup irq %d\n", irq);
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/* Enable timer0 interrupt */
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val = readl(timer_base + TIMER_IRQ_EN_REG);
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writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
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sun4i_clockevent.cpumask = cpumask_of(0);
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clockevents_config_and_register(&sun4i_clockevent, rate / TIMER_SCAL,
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0x1, 0xff);
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}
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CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
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sun4i_timer_init);
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