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https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
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249ac17e96
The attached patches provides part 4 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
315 lines
6.9 KiB
ArmAsm
315 lines
6.9 KiB
ArmAsm
/*
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* arch/xtensa/lib/hal/memcopy.S -- Core HAL library functions
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* xthal_memcpy and xthal_bcopy
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2002 - 2005 Tensilica Inc.
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*/
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#include <xtensa/coreasm.h>
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.macro src_b r, w0, w1
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#ifdef __XTENSA_EB__
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src \r, \w0, \w1
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#else
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src \r, \w1, \w0
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#endif
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.endm
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.macro ssa8 r
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#ifdef __XTENSA_EB__
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ssa8b \r
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#else
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ssa8l \r
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#endif
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.endm
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/*
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* void *memcpy(void *dst, const void *src, size_t len);
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* void *memmove(void *dst, const void *src, size_t len);
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* void *bcopy(const void *src, void *dst, size_t len);
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*
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* This function is intended to do the same thing as the standard
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* library function memcpy() (or bcopy()) for most cases.
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* However, where the source and/or destination references
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* an instruction RAM or ROM or a data RAM or ROM, that
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* source and/or destination will always be accessed with
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* 32-bit load and store instructions (as required for these
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* types of devices).
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*
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* !!!!!!! XTFIXME:
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* !!!!!!! Handling of IRAM/IROM has not yet
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* !!!!!!! been implemented.
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*
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* The bcopy version is provided here to avoid the overhead
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* of an extra call, for callers that require this convention.
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*
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* The (general case) algorithm is as follows:
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* If destination is unaligned, align it by conditionally
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* copying 1 and 2 bytes.
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* If source is aligned,
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* do 16 bytes with a loop, and then finish up with
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* 8, 4, 2, and 1 byte copies conditional on the length;
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* else (if source is unaligned),
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* do the same, but use SRC to align the source data.
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* This code tries to use fall-through branches for the common
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* case of aligned source and destination and multiple
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* of 4 (or 8) length.
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*
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* Register use:
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* a0/ return address
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* a1/ stack pointer
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* a2/ return value
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* a3/ src
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* a4/ length
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* a5/ dst
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* a6/ tmp
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* a7/ tmp
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* a8/ tmp
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* a9/ tmp
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* a10/ tmp
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* a11/ tmp
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*/
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.text
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.align 4
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.global bcopy
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.type bcopy,@function
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bcopy:
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entry sp, 16 # minimal stack frame
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# a2=src, a3=dst, a4=len
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mov a5, a3 # copy dst so that a2 is return value
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mov a3, a2
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mov a2, a5
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j .Lcommon # go to common code for memcpy+bcopy
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/*
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* Byte by byte copy
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*/
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.align 4
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.byte 0 # 1 mod 4 alignment for LOOPNEZ
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# (0 mod 4 alignment for LBEG)
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.Lbytecopy:
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#if XCHAL_HAVE_LOOPS
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loopnez a4, .Lbytecopydone
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#else /* !XCHAL_HAVE_LOOPS */
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beqz a4, .Lbytecopydone
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add a7, a3, a4 # a7 = end address for source
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#endif /* !XCHAL_HAVE_LOOPS */
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.Lnextbyte:
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l8ui a6, a3, 0
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addi a3, a3, 1
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s8i a6, a5, 0
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addi a5, a5, 1
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#if !XCHAL_HAVE_LOOPS
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blt a3, a7, .Lnextbyte
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#endif /* !XCHAL_HAVE_LOOPS */
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.Lbytecopydone:
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retw
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/*
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* Destination is unaligned
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*/
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.align 4
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.Ldst1mod2: # dst is only byte aligned
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_bltui a4, 7, .Lbytecopy # do short copies byte by byte
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# copy 1 byte
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l8ui a6, a3, 0
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addi a3, a3, 1
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addi a4, a4, -1
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s8i a6, a5, 0
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addi a5, a5, 1
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_bbci.l a5, 1, .Ldstaligned # if dst is now aligned, then
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# return to main algorithm
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.Ldst2mod4: # dst 16-bit aligned
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# copy 2 bytes
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_bltui a4, 6, .Lbytecopy # do short copies byte by byte
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l8ui a6, a3, 0
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l8ui a7, a3, 1
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addi a3, a3, 2
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addi a4, a4, -2
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s8i a6, a5, 0
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s8i a7, a5, 1
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addi a5, a5, 2
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j .Ldstaligned # dst is now aligned, return to main algorithm
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.align 4
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.global memcpy
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.type memcpy,@function
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memcpy:
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.global memmove
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.type memmove,@function
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memmove:
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entry sp, 16 # minimal stack frame
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# a2/ dst, a3/ src, a4/ len
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mov a5, a2 # copy dst so that a2 is return value
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.Lcommon:
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_bbsi.l a2, 0, .Ldst1mod2 # if dst is 1 mod 2
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_bbsi.l a2, 1, .Ldst2mod4 # if dst is 2 mod 4
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.Ldstaligned: # return here from .Ldst?mod? once dst is aligned
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srli a7, a4, 4 # number of loop iterations with 16B
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# per iteration
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movi a8, 3 # if source is not aligned,
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_bany a3, a8, .Lsrcunaligned # then use shifting copy
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/*
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* Destination and source are word-aligned, use word copy.
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*/
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# copy 16 bytes per iteration for word-aligned dst and word-aligned src
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#if XCHAL_HAVE_LOOPS
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loopnez a7, .Loop1done
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#else /* !XCHAL_HAVE_LOOPS */
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beqz a7, .Loop1done
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slli a8, a7, 4
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add a8, a8, a3 # a8 = end of last 16B source chunk
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#endif /* !XCHAL_HAVE_LOOPS */
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.Loop1:
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l32i a6, a3, 0
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l32i a7, a3, 4
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s32i a6, a5, 0
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l32i a6, a3, 8
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s32i a7, a5, 4
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l32i a7, a3, 12
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s32i a6, a5, 8
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addi a3, a3, 16
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s32i a7, a5, 12
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addi a5, a5, 16
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#if !XCHAL_HAVE_LOOPS
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blt a3, a8, .Loop1
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#endif /* !XCHAL_HAVE_LOOPS */
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.Loop1done:
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bbci.l a4, 3, .L2
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# copy 8 bytes
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l32i a6, a3, 0
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l32i a7, a3, 4
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addi a3, a3, 8
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s32i a6, a5, 0
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s32i a7, a5, 4
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addi a5, a5, 8
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.L2:
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bbsi.l a4, 2, .L3
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bbsi.l a4, 1, .L4
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bbsi.l a4, 0, .L5
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retw
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.L3:
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# copy 4 bytes
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l32i a6, a3, 0
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addi a3, a3, 4
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s32i a6, a5, 0
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addi a5, a5, 4
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bbsi.l a4, 1, .L4
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bbsi.l a4, 0, .L5
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retw
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.L4:
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# copy 2 bytes
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l16ui a6, a3, 0
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addi a3, a3, 2
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s16i a6, a5, 0
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addi a5, a5, 2
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bbsi.l a4, 0, .L5
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retw
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.L5:
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# copy 1 byte
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l8ui a6, a3, 0
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s8i a6, a5, 0
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retw
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/*
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* Destination is aligned, Source is unaligned
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*/
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.align 4
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.Lsrcunaligned:
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_beqz a4, .Ldone # avoid loading anything for zero-length copies
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# copy 16 bytes per iteration for word-aligned dst and unaligned src
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ssa8 a3 # set shift amount from byte offset
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#define SIM_CHECKS_ALIGNMENT 1 /* set to 1 when running on ISS (simulator) with the
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lint or ferret client, or 0 to save a few cycles */
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#if XCHAL_UNALIGNED_LOAD_EXCEPTION || SIM_CHECKS_ALIGNMENT
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and a11, a3, a8 # save unalignment offset for below
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sub a3, a3, a11 # align a3
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#endif
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l32i a6, a3, 0 # load first word
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#if XCHAL_HAVE_LOOPS
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loopnez a7, .Loop2done
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#else /* !XCHAL_HAVE_LOOPS */
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beqz a7, .Loop2done
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slli a10, a7, 4
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add a10, a10, a3 # a10 = end of last 16B source chunk
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#endif /* !XCHAL_HAVE_LOOPS */
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.Loop2:
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l32i a7, a3, 4
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l32i a8, a3, 8
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src_b a6, a6, a7
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s32i a6, a5, 0
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l32i a9, a3, 12
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src_b a7, a7, a8
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s32i a7, a5, 4
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l32i a6, a3, 16
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src_b a8, a8, a9
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s32i a8, a5, 8
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addi a3, a3, 16
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src_b a9, a9, a6
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s32i a9, a5, 12
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addi a5, a5, 16
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#if !XCHAL_HAVE_LOOPS
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blt a3, a10, .Loop2
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#endif /* !XCHAL_HAVE_LOOPS */
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.Loop2done:
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bbci.l a4, 3, .L12
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# copy 8 bytes
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l32i a7, a3, 4
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l32i a8, a3, 8
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src_b a6, a6, a7
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s32i a6, a5, 0
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addi a3, a3, 8
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src_b a7, a7, a8
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s32i a7, a5, 4
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addi a5, a5, 8
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mov a6, a8
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.L12:
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bbci.l a4, 2, .L13
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# copy 4 bytes
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l32i a7, a3, 4
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addi a3, a3, 4
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src_b a6, a6, a7
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s32i a6, a5, 0
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addi a5, a5, 4
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mov a6, a7
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.L13:
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#if XCHAL_UNALIGNED_LOAD_EXCEPTION || SIM_CHECKS_ALIGNMENT
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add a3, a3, a11 # readjust a3 with correct misalignment
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#endif
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bbsi.l a4, 1, .L14
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bbsi.l a4, 0, .L15
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.Ldone: retw
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.L14:
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# copy 2 bytes
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l8ui a6, a3, 0
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l8ui a7, a3, 1
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addi a3, a3, 2
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s8i a6, a5, 0
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s8i a7, a5, 1
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addi a5, a5, 2
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bbsi.l a4, 0, .L15
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retw
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.L15:
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# copy 1 byte
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l8ui a6, a3, 0
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s8i a6, a5, 0
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retw
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/*
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* Local Variables:
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* mode:fundamental
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* comment-start: "# "
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* comment-start-skip: "# *"
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* End:
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*/
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