239 lines
7.2 KiB
C
239 lines
7.2 KiB
C
/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __MHL_SPEC_DEFS_H__
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#define __MHL_SPEC_DEFS_H__
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enum DevCapOffset_e {
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DEVCAP_OFFSET_DEV_STATE = 0x00,
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DEVCAP_OFFSET_MHL_VERSION = 0x01,
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DEVCAP_OFFSET_DEV_CAT = 0x02,
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DEVCAP_OFFSET_ADOPTER_ID_H = 0x03,
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DEVCAP_OFFSET_ADOPTER_ID_L = 0x04,
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DEVCAP_OFFSET_VID_LINK_MODE = 0x05,
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DEVCAP_OFFSET_AUD_LINK_MODE = 0x06,
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DEVCAP_OFFSET_VIDEO_TYPE = 0x07,
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DEVCAP_OFFSET_LOG_DEV_MAP = 0x08,
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DEVCAP_OFFSET_BANDWIDTH = 0x09,
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DEVCAP_OFFSET_FEATURE_FLAG = 0x0A,
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DEVCAP_OFFSET_DEVICE_ID_H = 0x0B,
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DEVCAP_OFFSET_DEVICE_ID_L = 0x0C,
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DEVCAP_OFFSET_SCRATCHPAD_SIZE = 0x0D,
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DEVCAP_OFFSET_INT_STAT_SIZE = 0x0E,
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DEVCAP_OFFSET_RESERVED = 0x0F,
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/* this one must be last */
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DEVCAP_SIZE
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};
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#ifndef __MHL_MSM_8334_REGS_H__
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#define __MHL_MSM_8334_REGS_H__
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#define BIT0 0x01
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#define BIT1 0x02
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#define BIT2 0x04
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#define BIT3 0x08
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#define BIT4 0x10
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#define BIT5 0x20
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#define BIT6 0x40
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#define BIT7 0x80
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#define LOW 0
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#define HIGH 1
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#define MAX_PAGES 8
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#endif
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/* Version that this chip supports*/
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/* bits 4..7 */
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#define MHL_VER_MAJOR (0x01 << 4)
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/* bits 0..3 */
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#define MHL_VER_MINOR 0x02
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#define MHL_VERSION (MHL_VER_MAJOR | MHL_VER_MINOR)
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/*Device Category*/
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#define MHL_DEV_CATEGORY_OFFSET DEVCAP_OFFSET_DEV_CAT
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#define MHL_DEV_CATEGORY_POW_BIT (BIT4)
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#define MHL_DEV_CAT_SOURCE 0x02
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/*Video Link Mode*/
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#define MHL_DEV_VID_LINK_SUPPRGB444 0x01
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#define MHL_DEV_VID_LINK_SUPPYCBCR444 0x02
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#define MHL_DEV_VID_LINK_SUPPYCBCR422 0x04
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#define MHL_DEV_VID_LINK_SUPP_PPIXEL 0x08
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#define MHL_DEV_VID_LINK_SUPP_ISLANDS 0x10
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/*Audio Link Mode Support*/
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#define MHL_DEV_AUD_LINK_2CH 0x01
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#define MHL_DEV_AUD_LINK_8CH 0x02
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/*Feature Flag in the devcap*/
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#define MHL_DEV_FEATURE_FLAG_OFFSET DEVCAP_OFFSET_FEATURE_FLAG
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/* Dongles have freedom to not support RCP */
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#define MHL_FEATURE_RCP_SUPPORT BIT0
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/* Dongles have freedom to not support RAP */
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#define MHL_FEATURE_RAP_SUPPORT BIT1
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/* Dongles have freedom to not support SCRATCHPAD */
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#define MHL_FEATURE_SP_SUPPORT BIT2
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/*Logical Dev Map*/
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#define MHL_DEV_LD_DISPLAY (0x01 << 0)
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#define MHL_DEV_LD_VIDEO (0x01 << 1)
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#define MHL_DEV_LD_AUDIO (0x01 << 2)
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#define MHL_DEV_LD_MEDIA (0x01 << 3)
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#define MHL_DEV_LD_TUNER (0x01 << 4)
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#define MHL_DEV_LD_RECORD (0x01 << 5)
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#define MHL_DEV_LD_SPEAKER (0x01 << 6)
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#define MHL_DEV_LD_GUI (0x01 << 7)
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/*Bandwidth*/
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/* 225 MHz */
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#define MHL_BANDWIDTH_LIMIT 22
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#define MHL_STATUS_REG_CONNECTED_RDY 0x30
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#define MHL_STATUS_REG_LINK_MODE 0x31
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#define MHL_STATUS_DCAP_RDY BIT0
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#define MHL_STATUS_CLK_MODE_MASK 0x07
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#define MHL_STATUS_CLK_MODE_PACKED_PIXEL 0x02
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#define MHL_STATUS_CLK_MODE_NORMAL 0x03
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#define MHL_STATUS_PATH_EN_MASK 0x08
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#define MHL_STATUS_PATH_ENABLED 0x08
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#define MHL_STATUS_PATH_DISABLED 0x00
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#define MHL_STATUS_MUTED_MASK 0x10
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#define MHL_RCHANGE_INT 0x20
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#define MHL_DCHANGE_INT 0x21
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#define MHL_INT_DCAP_CHG BIT0
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#define MHL_INT_DSCR_CHG BIT1
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#define MHL_INT_REQ_WRT BIT2
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#define MHL_INT_GRT_WRT BIT3
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/* On INTR_1 the EDID_CHG is located at BIT 0*/
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#define MHL_INT_EDID_CHG BIT1
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/* This contains one nibble each - max offset */
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#define MHL_INT_AND_STATUS_SIZE 0x33
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#define MHL_SCRATCHPAD_OFFSET 0x40
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#define MHL_SCRATCHPAD_SIZE 16
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#define MAX_SCRATCHPAD_TRANSFER_SIZE 64
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#define ADOPTER_ID_SIZE 2
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#define MHL_DEVCAP_ALL 0xffff
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/* manually define highest number */
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#define MHL_MAX_BUFFER_SIZE MHL_SCRATCHPAD_SIZE
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#define MHL_BURST_WAIT (1000)
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enum {
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/* RCP sub-command */
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MHL_MSC_MSG_RCP = 0x10,
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/* RCP Acknowledge sub-command */
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MHL_MSC_MSG_RCPK = 0x11,
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/* RCP Error sub-command */
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MHL_MSC_MSG_RCPE = 0x12,
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/* Mode Change Warning sub-command */
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MHL_MSC_MSG_RAP = 0x20,
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/* MCW Acknowledge sub-command */
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MHL_MSC_MSG_RAPK = 0x21,
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};
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#define MHL_RCPE_NO_ERROR 0x00
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#define MHL_RCPE_UNSUPPORTED_KEY_CODE 0x01
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#define MHL_RCPE_INEFFECTIVE_KEY_CODE 0x01
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#define MHL_RCPE_BUSY 0x02
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#define MHL_RAPK_NO_ERROR 0x00
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#define MHL_RAPK_UNRECOGNIZED_ACTION_CODE 0x01
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#define MHL_RAPK_UNSUPPORTED_ACTION_CODE 0x02
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#define MHL_RAPK_BUSY 0x03
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#define T_ABORT_NEXT (2050)
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/* MHL spec related defines*/
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enum {
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/* Command or Data byte acknowledge */
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MHL_ACK = 0x33,
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/* Command or Data byte not acknowledge */
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MHL_NACK = 0x34,
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/* Transaction abort */
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MHL_ABORT = 0x35,
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/* 0xE0 - Write one status register strip top bit */
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MHL_WRITE_STAT = 0x60 | 0x80,
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/* Write one interrupt register */
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MHL_SET_INT = 0x60,
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/* Read one register */
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MHL_READ_DEVCAP = 0x61,
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/* Read CBUS revision level from follower */
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MHL_GET_STATE = 0x62,
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/* Read vendor ID value from follower. */
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MHL_GET_VENDOR_ID = 0x63,
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/* Set Hot Plug Detect in follower */
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MHL_SET_HPD = 0x64,
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/* Clear Hot Plug Detect in follower */
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MHL_CLR_HPD = 0x65,
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/* Set Capture ID for downstream device. */
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MHL_SET_CAP_ID = 0x66,
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/* Get Capture ID from downstream device. */
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MHL_GET_CAP_ID = 0x67,
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/* VS command to send RCP sub-commands */
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MHL_MSC_MSG = 0x68,
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/* Get Vendor-Specific command error code. */
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MHL_GET_SC1_ERRORCODE = 0x69,
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/* Get DDC channel command error code. */
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MHL_GET_DDC_ERRORCODE = 0x6A,
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/* Get MSC command error code. */
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MHL_GET_MSC_ERRORCODE = 0x6B,
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/* Write 1-16 bytes to responder's scratchpad. */
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MHL_WRITE_BURST = 0x6C,
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/* Get channel 3 command error code. */
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MHL_GET_SC3_ERRORCODE = 0x6D,
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};
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/* Polling. */
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#define MHL_RAP_POLL 0x00
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/* Turn content streaming ON. */
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#define MHL_RAP_CONTENT_ON 0x10
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/* Turn content streaming OFF. */
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#define MHL_RAP_CONTENT_OFF 0x11
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/*
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*
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* MHL Timings applicable to this driver.
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*
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*/
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/* 100 - 1000 milliseconds. Per MHL 1.0 Specs */
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#define T_SRC_VBUS_CBUS_TO_STABLE (200)
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/* 20 milliseconds. Per MHL 1.0 Specs */
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#define T_SRC_WAKE_PULSE_WIDTH_1 (20)
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/* 60 milliseconds. Per MHL 1.0 Specs */
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#define T_SRC_WAKE_PULSE_WIDTH_2 (60)
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/* 100 - 1000 milliseconds. Per MHL 1.0 Specs */
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#define T_SRC_WAKE_TO_DISCOVER (500)
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#define T_SRC_VBUS_CBUS_T0_STABLE (500)
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/* Allow RSEN to stay low this much before reacting.*/
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#define T_SRC_RSEN_DEGLITCH (100)
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/* Wait this much after connection before reacting to RSEN (300-500ms)*/
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/* Per specs between 300 to 500 ms*/
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#define T_SRC_RXSENSE_CHK (400)
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#endif /* __MHL_SPEC_DEFS_H__ */
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