mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-10-20 18:39:12 +00:00
4e57b68178
I recently picked up my older work to remove unnecessary #includes of sched.h, starting from a patch by Dave Jones to not include sched.h from module.h. This reduces the number of indirect includes of sched.h by ~300. Another ~400 pointless direct includes can be removed after this disentangling (patch to follow later). However, quite a few indirect includes need to be fixed up for this. In order to feed the patches through -mm with as little disturbance as possible, I've split out the fixes I accumulated up to now (complete for i386 and x86_64, more archs to follow later) and post them before the real patch. This way this large part of the patch is kept simple with only adding #includes, and all hunks are independent of each other. So if any hunk rejects or gets in the way of other patches, just drop it. My scripts will pick it up again in the next round. Signed-off-by: Tim Schmielau <tim@physik3.uni-rostock.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
358 lines
8.7 KiB
C
358 lines
8.7 KiB
C
/*
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* linux/arch/arm/mach-integrator/integrator_ap.c
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*
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* Copyright (C) 2000-2003 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/sysdev.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/setup.h>
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#include <asm/param.h> /* HZ */
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#include <asm/mach-types.h>
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#include <asm/hardware/amba.h>
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#include <asm/hardware/amba_kmi.h>
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#include <asm/arch/lm.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/flash.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include "common.h"
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/*
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* All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
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* is the (PA >> 12).
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*
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* Setup a VA for the Integrator interrupt controller (for header #0,
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* just for now).
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*/
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#define VA_IC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE)
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#define VA_SC_BASE IO_ADDRESS(INTEGRATOR_SC_BASE)
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#define VA_EBI_BASE IO_ADDRESS(INTEGRATOR_EBI_BASE)
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#define VA_CMIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE) + INTEGRATOR_HDR_IC_OFFSET
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/*
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* Logical Physical
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* e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
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* ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
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* ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k)
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* ee000000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
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* ef000000 Cache flush
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* f1000000 10000000 Core module registers
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* f1100000 11000000 System controller registers
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* f1200000 12000000 EBI registers
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* f1300000 13000000 Counter/Timer
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* f1400000 14000000 Interrupt controller
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* f1600000 16000000 UART 0
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* f1700000 17000000 UART 1
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* f1a00000 1a000000 Debug LEDs
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* f1b00000 1b000000 GPIO
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*/
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static struct map_desc ap_io_desc[] __initdata = {
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{
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.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_GPIO_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_GPIO_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = PCI_MEMORY_VADDR,
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.pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
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.length = SZ_16M,
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.type = MT_DEVICE
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}, {
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.virtual = PCI_CONFIG_VADDR,
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.pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
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.length = SZ_16M,
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.type = MT_DEVICE
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}, {
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.virtual = PCI_V3_VADDR,
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.pfn = __phys_to_pfn(PHYS_PCI_V3_BASE),
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.length = SZ_64K,
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.type = MT_DEVICE
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}, {
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.virtual = PCI_IO_VADDR,
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.pfn = __phys_to_pfn(PHYS_PCI_IO_BASE),
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.length = SZ_64K,
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.type = MT_DEVICE
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}
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};
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static void __init ap_map_io(void)
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{
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iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
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}
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#define INTEGRATOR_SC_VALID_INT 0x003fffff
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static void sc_mask_irq(unsigned int irq)
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{
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writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_CLEAR);
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}
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static void sc_unmask_irq(unsigned int irq)
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{
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writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_SET);
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}
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static struct irqchip sc_chip = {
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.ack = sc_mask_irq,
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.mask = sc_mask_irq,
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.unmask = sc_unmask_irq,
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};
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static void __init ap_init_irq(void)
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{
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unsigned int i;
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/* Disable all interrupts initially. */
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/* Do the core module ones */
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writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
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/* do the header card stuff next */
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writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
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writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
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for (i = 0; i < NR_IRQS; i++) {
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if (((1 << i) & INTEGRATOR_SC_VALID_INT) != 0) {
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set_irq_chip(i, &sc_chip);
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set_irq_handler(i, do_level_IRQ);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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}
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}
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}
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#ifdef CONFIG_PM
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static unsigned long ic_irq_enable;
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static int irq_suspend(struct sys_device *dev, pm_message_t state)
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{
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ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
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return 0;
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}
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static int irq_resume(struct sys_device *dev)
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{
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/* disable all irq sources */
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writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
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writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
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writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
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writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
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return 0;
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}
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#else
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#define irq_suspend NULL
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#define irq_resume NULL
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#endif
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static struct sysdev_class irq_class = {
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set_kset_name("irq"),
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.suspend = irq_suspend,
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.resume = irq_resume,
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};
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static struct sys_device irq_device = {
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.id = 0,
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.cls = &irq_class,
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};
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static int __init irq_init_sysfs(void)
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{
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int ret = sysdev_class_register(&irq_class);
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if (ret == 0)
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ret = sysdev_register(&irq_device);
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return ret;
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}
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device_initcall(irq_init_sysfs);
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/*
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* Flash handling.
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*/
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#define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
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#define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
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#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
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#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
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static int ap_flash_init(void)
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{
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u32 tmp;
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writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
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tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
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writel(tmp, EBI_CSR1);
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if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
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writel(0xa05f, EBI_LOCK);
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writel(tmp, EBI_CSR1);
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writel(0, EBI_LOCK);
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}
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return 0;
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}
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static void ap_flash_exit(void)
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{
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u32 tmp;
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writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
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tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
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writel(tmp, EBI_CSR1);
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if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
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writel(0xa05f, EBI_LOCK);
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writel(tmp, EBI_CSR1);
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writel(0, EBI_LOCK);
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}
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}
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static void ap_flash_set_vpp(int on)
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{
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unsigned long reg = on ? SC_CTRLS : SC_CTRLC;
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writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
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}
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static struct flash_platform_data ap_flash_data = {
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.map_name = "cfi_probe",
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.width = 4,
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.init = ap_flash_init,
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.exit = ap_flash_exit,
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.set_vpp = ap_flash_set_vpp,
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};
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static struct resource cfi_flash_resource = {
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.start = INTEGRATOR_FLASH_BASE,
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.end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device cfi_flash_device = {
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.name = "armflash",
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.id = 0,
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.dev = {
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.platform_data = &ap_flash_data,
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},
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.num_resources = 1,
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.resource = &cfi_flash_resource,
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};
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static void __init ap_init(void)
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{
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unsigned long sc_dec;
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int i;
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platform_device_register(&cfi_flash_device);
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sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
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for (i = 0; i < 4; i++) {
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struct lm_device *lmdev;
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if ((sc_dec & (16 << i)) == 0)
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continue;
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lmdev = kmalloc(sizeof(struct lm_device), GFP_KERNEL);
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if (!lmdev)
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continue;
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memset(lmdev, 0, sizeof(struct lm_device));
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lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
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lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
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lmdev->resource.flags = IORESOURCE_MEM;
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lmdev->irq = IRQ_AP_EXPINT0 + i;
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lmdev->id = i;
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lm_device_register(lmdev);
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}
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}
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static void __init ap_init_timer(void)
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{
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integrator_time_init(1000000 * TICKS_PER_uSEC / HZ, 0);
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}
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static struct sys_timer ap_timer = {
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.init = ap_init_timer,
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.offset = integrator_gettimeoffset,
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};
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MACHINE_START(INTEGRATOR, "ARM-Integrator")
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/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
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.phys_ram = 0x00000000,
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.phys_io = 0x16000000,
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.io_pg_offst = ((0xf1600000) >> 18) & 0xfffc,
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.boot_params = 0x00000100,
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.map_io = ap_map_io,
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.init_irq = ap_init_irq,
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.timer = &ap_timer,
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.init_machine = ap_init,
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MACHINE_END
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