mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-10-01 09:16:06 +00:00
6004e1b7ef
Here's a patch that builds on Natalie Protasevich's IRQ compression patch and tries to work for MPS boots as well as ACPI. It is meant for a 4-node IBM x460 NUMA box, which was dying because it had interrupt pins with GSI numbers > NR_IRQS and thus overflowed irq_desc. The problem is that this system has 270 GSIs (which are 1:1 mapped with I/O APIC RTEs) and an 8-node box would have 540. This is much bigger than NR_IRQS (224 for both i386 and x86_64). Also, there aren't enough vectors to go around. There are about 190 usable vectors, not counting the reserved ones and the unused vectors at 0x20 to 0x2F. So, my patch attempts to compress the GSI range and share vectors by sharing IRQs. Cc: "Protasevich, Natalie" <Natalie.Protasevich@unisys.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
242 lines
6.6 KiB
C
242 lines
6.6 KiB
C
#ifndef __ASM_MPSPEC_H
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#define __ASM_MPSPEC_H
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/*
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* Structure definitions for SMP machines following the
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* Intel Multiprocessing Specification 1.1 and 1.4.
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*/
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/*
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* This tag identifies where the SMP configuration
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* information is.
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*/
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#define SMP_MAGIC_IDENT (('_'<<24)|('P'<<16)|('M'<<8)|'_')
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/*
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* A maximum of 255 APICs with the current APIC ID architecture.
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*/
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#define MAX_APICS 128
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struct intel_mp_floating
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{
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char mpf_signature[4]; /* "_MP_" */
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unsigned int mpf_physptr; /* Configuration table address */
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unsigned char mpf_length; /* Our length (paragraphs) */
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unsigned char mpf_specification;/* Specification version */
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unsigned char mpf_checksum; /* Checksum (makes sum 0) */
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unsigned char mpf_feature1; /* Standard or configuration ? */
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unsigned char mpf_feature2; /* Bit7 set for IMCR|PIC */
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unsigned char mpf_feature3; /* Unused (0) */
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unsigned char mpf_feature4; /* Unused (0) */
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unsigned char mpf_feature5; /* Unused (0) */
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};
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struct mp_config_table
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{
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char mpc_signature[4];
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#define MPC_SIGNATURE "PCMP"
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unsigned short mpc_length; /* Size of table */
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char mpc_spec; /* 0x01 */
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char mpc_checksum;
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char mpc_oem[8];
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char mpc_productid[12];
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unsigned int mpc_oemptr; /* 0 if not present */
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unsigned short mpc_oemsize; /* 0 if not present */
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unsigned short mpc_oemcount;
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unsigned int mpc_lapic; /* APIC address */
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unsigned int reserved;
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};
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/* Followed by entries */
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#define MP_PROCESSOR 0
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#define MP_BUS 1
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#define MP_IOAPIC 2
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#define MP_INTSRC 3
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#define MP_LINTSRC 4
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struct mpc_config_processor
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{
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unsigned char mpc_type;
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unsigned char mpc_apicid; /* Local APIC number */
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unsigned char mpc_apicver; /* Its versions */
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unsigned char mpc_cpuflag;
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#define CPU_ENABLED 1 /* Processor is available */
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#define CPU_BOOTPROCESSOR 2 /* Processor is the BP */
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unsigned int mpc_cpufeature;
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#define CPU_STEPPING_MASK 0x0F
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#define CPU_MODEL_MASK 0xF0
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#define CPU_FAMILY_MASK 0xF00
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unsigned int mpc_featureflag; /* CPUID feature value */
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unsigned int mpc_reserved[2];
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};
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struct mpc_config_bus
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{
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unsigned char mpc_type;
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unsigned char mpc_busid;
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unsigned char mpc_bustype[6] __attribute((packed));
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};
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/* List of Bus Type string values, Intel MP Spec. */
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#define BUSTYPE_EISA "EISA"
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#define BUSTYPE_ISA "ISA"
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#define BUSTYPE_INTERN "INTERN" /* Internal BUS */
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#define BUSTYPE_MCA "MCA"
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#define BUSTYPE_VL "VL" /* Local bus */
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#define BUSTYPE_PCI "PCI"
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#define BUSTYPE_PCMCIA "PCMCIA"
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#define BUSTYPE_CBUS "CBUS"
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#define BUSTYPE_CBUSII "CBUSII"
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#define BUSTYPE_FUTURE "FUTURE"
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#define BUSTYPE_MBI "MBI"
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#define BUSTYPE_MBII "MBII"
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#define BUSTYPE_MPI "MPI"
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#define BUSTYPE_MPSA "MPSA"
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#define BUSTYPE_NUBUS "NUBUS"
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#define BUSTYPE_TC "TC"
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#define BUSTYPE_VME "VME"
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#define BUSTYPE_XPRESS "XPRESS"
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struct mpc_config_ioapic
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{
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unsigned char mpc_type;
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unsigned char mpc_apicid;
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unsigned char mpc_apicver;
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unsigned char mpc_flags;
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#define MPC_APIC_USABLE 0x01
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unsigned int mpc_apicaddr;
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};
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struct mpc_config_intsrc
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{
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unsigned char mpc_type;
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unsigned char mpc_irqtype;
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unsigned short mpc_irqflag;
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unsigned char mpc_srcbus;
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unsigned char mpc_srcbusirq;
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unsigned char mpc_dstapic;
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unsigned char mpc_dstirq;
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};
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enum mp_irq_source_types {
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mp_INT = 0,
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mp_NMI = 1,
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mp_SMI = 2,
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mp_ExtINT = 3
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};
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#define MP_IRQDIR_DEFAULT 0
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#define MP_IRQDIR_HIGH 1
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#define MP_IRQDIR_LOW 3
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struct mpc_config_lintsrc
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{
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unsigned char mpc_type;
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unsigned char mpc_irqtype;
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unsigned short mpc_irqflag;
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unsigned char mpc_srcbusid;
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unsigned char mpc_srcbusirq;
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unsigned char mpc_destapic;
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#define MP_APIC_ALL 0xFF
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unsigned char mpc_destapiclint;
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};
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/*
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* Default configurations
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*
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* 1 2 CPU ISA 82489DX
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* 2 2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining
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* 3 2 CPU EISA 82489DX
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* 4 2 CPU MCA 82489DX
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* 5 2 CPU ISA+PCI
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* 6 2 CPU EISA+PCI
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* 7 2 CPU MCA+PCI
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*/
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#define MAX_MP_BUSSES 256
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/* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */
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#define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4)
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enum mp_bustype {
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MP_BUS_ISA = 1,
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MP_BUS_EISA,
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MP_BUS_PCI,
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MP_BUS_MCA
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};
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extern unsigned char mp_bus_id_to_type [MAX_MP_BUSSES];
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extern int mp_bus_id_to_pci_bus [MAX_MP_BUSSES];
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extern unsigned int boot_cpu_physical_apicid;
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extern int smp_found_config;
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extern void find_smp_config (void);
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extern void get_smp_config (void);
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extern int nr_ioapics;
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extern int apic_version [MAX_APICS];
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extern int mp_irq_entries;
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extern struct mpc_config_intsrc mp_irqs [MAX_IRQ_SOURCES];
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extern int mpc_default_type;
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extern unsigned long mp_lapic_addr;
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extern int pic_mode;
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#ifdef CONFIG_ACPI
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extern void mp_register_lapic (u8 id, u8 enabled);
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extern void mp_register_lapic_address (u64 address);
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#ifdef CONFIG_X86_IO_APIC
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extern void mp_register_ioapic (u8 id, u32 address, u32 gsi_base);
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extern void mp_override_legacy_irq (u8 bus_irq, u8 polarity, u8 trigger, u32 gsi);
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extern void mp_config_acpi_legacy_irqs (void);
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extern int mp_register_gsi (u32 gsi, int edge_level, int active_high_low);
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#endif /*CONFIG_X86_IO_APIC*/
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#endif
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extern int using_apic_timer;
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#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS)
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struct physid_mask
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{
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unsigned long mask[PHYSID_ARRAY_SIZE];
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};
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typedef struct physid_mask physid_mask_t;
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#define physid_set(physid, map) set_bit(physid, (map).mask)
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#define physid_clear(physid, map) clear_bit(physid, (map).mask)
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#define physid_isset(physid, map) test_bit(physid, (map).mask)
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#define physid_test_and_set(physid, map) test_and_set_bit(physid, (map).mask)
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#define physids_and(dst, src1, src2) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
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#define physids_or(dst, src1, src2) bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
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#define physids_clear(map) bitmap_zero((map).mask, MAX_APICS)
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#define physids_complement(dst, src) bitmap_complement((dst).mask, (src).mask, MAX_APICS)
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#define physids_empty(map) bitmap_empty((map).mask, MAX_APICS)
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#define physids_equal(map1, map2) bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
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#define physids_weight(map) bitmap_weight((map).mask, MAX_APICS)
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#define physids_shift_right(d, s, n) bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS)
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#define physids_shift_left(d, s, n) bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
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#define physids_coerce(map) ((map).mask[0])
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#define physids_promote(physids) \
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({ \
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physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
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__physid_mask.mask[0] = physids; \
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__physid_mask; \
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})
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#define physid_mask_of_physid(physid) \
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({ \
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physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
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physid_set(physid, __physid_mask); \
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__physid_mask; \
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})
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#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
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#define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
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extern physid_mask_t phys_cpu_present_map;
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#endif
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