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610142927b
The problem: After moving an interrupt when is it safe to teardown the data structures for receiving the interrupt at the old location? With a normal pci device it is possible to issue a read to a device to flush all posted writes. This does not work for the oldest ioapics because they are on a 3-wire apic bus which is a completely different data path. For some more modern ioapics when everything is using front side bus delivery you can flush interrupts by simply issuing a read to the ioapic. For other modern ioapics emperical testing has shown that this does not work. So it appears the only reliable way to know the last of the irqs from an ioapic have been received from before the ioapic was reprogrammed is to received the first irq from the ioapic from after it was reprogrammed. Once we know the last irq message has been received from an ioapic into a local apic we then need to know that irq message has been processed through the local apics. Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
155 lines
4.2 KiB
C
155 lines
4.2 KiB
C
#ifndef _ASM_HW_IRQ_H
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#define _ASM_HW_IRQ_H
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/*
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* linux/include/asm/hw_irq.h
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*
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* (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar
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*
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* moved some of the old arch/i386/kernel/irq.h to here. VY
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*
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* IRQ/IPI changes taken from work by Thomas Radke
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* <tomsoft@informatik.tu-chemnitz.de>
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*
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* hacked by Andi Kleen for x86-64.
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*/
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#ifndef __ASSEMBLY__
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#include <asm/atomic.h>
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#include <asm/irq.h>
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#include <linux/profile.h>
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#include <linux/smp.h>
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#include <linux/percpu.h>
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#endif
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#define NMI_VECTOR 0x02
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/*
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* IDT vectors usable for external interrupt sources start
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* at 0x20:
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*/
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#define FIRST_EXTERNAL_VECTOR 0x20
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#define IA32_SYSCALL_VECTOR 0x80
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/* Reserve the lowest usable priority level 0x20 - 0x2f for triggering
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* cleanup after irq migration.
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*/
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#define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR
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/*
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* Vectors 0x20-0x2f are used for ISA interrupts.
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*/
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#define IRQ0_VECTOR FIRST_EXTERNAL_VECTOR + 0x10
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#define IRQ1_VECTOR IRQ0_VECTOR + 1
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#define IRQ2_VECTOR IRQ0_VECTOR + 2
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#define IRQ3_VECTOR IRQ0_VECTOR + 3
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#define IRQ4_VECTOR IRQ0_VECTOR + 4
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#define IRQ5_VECTOR IRQ0_VECTOR + 5
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#define IRQ6_VECTOR IRQ0_VECTOR + 6
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#define IRQ7_VECTOR IRQ0_VECTOR + 7
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#define IRQ8_VECTOR IRQ0_VECTOR + 8
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#define IRQ9_VECTOR IRQ0_VECTOR + 9
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#define IRQ10_VECTOR IRQ0_VECTOR + 10
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#define IRQ11_VECTOR IRQ0_VECTOR + 11
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#define IRQ12_VECTOR IRQ0_VECTOR + 12
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#define IRQ13_VECTOR IRQ0_VECTOR + 13
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#define IRQ14_VECTOR IRQ0_VECTOR + 14
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#define IRQ15_VECTOR IRQ0_VECTOR + 15
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/*
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* Special IRQ vectors used by the SMP architecture, 0xf0-0xff
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*
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* some of the following vectors are 'rare', they are merged
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* into a single vector (CALL_FUNCTION_VECTOR) to save vector space.
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* TLB, reschedule and local APIC vectors are performance-critical.
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*/
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#define SPURIOUS_APIC_VECTOR 0xff
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#define ERROR_APIC_VECTOR 0xfe
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#define RESCHEDULE_VECTOR 0xfd
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#define CALL_FUNCTION_VECTOR 0xfc
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/* fb free - please don't readd KDB here because it's useless
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(hint - think what a NMI bit does to a vector) */
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#define THERMAL_APIC_VECTOR 0xfa
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#define THRESHOLD_APIC_VECTOR 0xf9
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/* f8 free */
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#define INVALIDATE_TLB_VECTOR_END 0xf7
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#define INVALIDATE_TLB_VECTOR_START 0xf0 /* f0-f7 used for TLB flush */
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#define NUM_INVALIDATE_TLB_VECTORS 8
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/*
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* Local APIC timer IRQ vector is on a different priority level,
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* to work around the 'lost local interrupt if more than 2 IRQ
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* sources per level' errata.
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*/
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#define LOCAL_TIMER_VECTOR 0xef
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/*
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* First APIC vector available to drivers: (vectors 0x30-0xee)
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* we start at 0x41 to spread out vectors evenly between priority
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* levels. (0x80 is the syscall vector)
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*/
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#define FIRST_DEVICE_VECTOR (IRQ15_VECTOR + 2)
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#define FIRST_SYSTEM_VECTOR 0xef /* duplicated in irq.h */
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#ifndef __ASSEMBLY__
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typedef int vector_irq_t[NR_VECTORS];
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DECLARE_PER_CPU(vector_irq_t, vector_irq);
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extern void __setup_vector_irq(int cpu);
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extern spinlock_t vector_lock;
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/*
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* Various low-level irq details needed by irq.c, process.c,
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* time.c, io_apic.c and smp.c
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*
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* Interrupt entry/exit code at both C and assembly level
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*/
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extern void disable_8259A_irq(unsigned int irq);
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extern void enable_8259A_irq(unsigned int irq);
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extern int i8259A_irq_pending(unsigned int irq);
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extern void make_8259A_irq(unsigned int irq);
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extern void init_8259A(int aeoi);
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extern void send_IPI_self(int vector);
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extern void init_VISWS_APIC_irqs(void);
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extern void setup_IO_APIC(void);
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extern void disable_IO_APIC(void);
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extern void print_IO_APIC(void);
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extern int IO_APIC_get_PCI_irq_vector(int bus, int slot, int fn);
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extern void send_IPI(int dest, int vector);
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extern void setup_ioapic_dest(void);
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extern unsigned long io_apic_irqs;
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extern atomic_t irq_err_count;
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extern atomic_t irq_mis_count;
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#define IO_APIC_IRQ(x) (((x) >= 16) || ((1<<(x)) & io_apic_irqs))
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#define __STR(x) #x
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#define STR(x) __STR(x)
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#include <asm/ptrace.h>
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#define IRQ_NAME2(nr) nr##_interrupt(void)
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#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
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/*
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* SMP has a few special interrupts for IPI messages
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*/
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#define BUILD_IRQ(nr) \
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asmlinkage void IRQ_NAME(nr); \
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__asm__( \
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"\n.p2align\n" \
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"IRQ" #nr "_interrupt:\n\t" \
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"push $~(" #nr ") ; " \
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"jmp common_interrupt");
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#define platform_legacy_irq(irq) ((irq) < 16)
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#endif
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#endif /* _ASM_HW_IRQ_H */
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