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6504cf3412
While testing mpc512x-dma driver with dmatest module I've found that
I can hang the mpc512x-dma issuing request from multiple threads to
the single channel.
insmod dmatest.ko max_channels=1 threads_per_chan=16
After investigating this case I've managed to find that this happens
if and only if we have more than one queued requests.
In this case the driver tries to make use of hardware scatter/gather
functionality. I've found two problems with scatter/gather:
1. When TCD is copied form RAM to the TCD register space with memcpy_io()
e_sg bit eventually gets cleared. This results in only first TCD being
executed. I've added setting of e_sg bit explicitly in the TCD registers.
BTW, what is the correct way to do this? (How can I use setbits with bitfield
structure?) After that hardware loads consecutive TCDs and we hit the
second issue.
2. Existing code clears int_maj bit in the last TCD so we never get
an interrupt on transfer completion.
With these fixes my tests with many threads of single channel succeed but
tests that use many channels simultaneously still don't work reliable.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Acked-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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|---|---|---|
| .. | ||
| ioat | ||
| ipu | ||
| ppc4xx | ||
| amba-pl08x.c | ||
| at_hdmac.c | ||
| at_hdmac_regs.h | ||
| coh901318.c | ||
| coh901318_lli.c | ||
| coh901318_lli.h | ||
| dmaengine.c | ||
| dmatest.c | ||
| dw_dmac.c | ||
| dw_dmac_regs.h | ||
| fsldma.c | ||
| fsldma.h | ||
| imx-dma.c | ||
| imx-sdma.c | ||
| intel_mid_dma.c | ||
| intel_mid_dma_regs.h | ||
| iop-adma.c | ||
| iovlock.c | ||
| Kconfig | ||
| Makefile | ||
| mpc512x_dma.c | ||
| mv_xor.c | ||
| mv_xor.h | ||
| pch_dma.c | ||
| pl330.c | ||
| shdma.c | ||
| shdma.h | ||
| ste_dma40.c | ||
| ste_dma40_ll.c | ||
| ste_dma40_ll.h | ||
| timb_dma.c | ||
| txx9dmac.c | ||
| txx9dmac.h | ||