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https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
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c6e58ebb37
Patch from Ben Dooks The IRQ_EINT0 through IRQ_EINT3 handling has changed on the S3C2412 from the previous SoCs in the range, and thus we need to add code to handle this. The changes come about due to these IRQs being displayed in two different registers, and needing to be acked and masked in both. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
104 lines
2.5 KiB
C
104 lines
2.5 KiB
C
/* arch/arm/mach-s3c2410/irq.h
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*
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* Copyright (c) 2004-2005 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* Header file for S3C24XX CPU IRQ support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Modifications:
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*/
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#define irqdbf(x...)
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#define irqdbf2(x...)
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#define EXTINT_OFF (IRQ_EINT4 - 4)
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extern struct irqchip s3c_irq_level_chip;
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static inline void
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s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
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int subcheck)
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{
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unsigned long mask;
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unsigned long submask;
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submask = __raw_readl(S3C2410_INTSUBMSK);
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mask = __raw_readl(S3C2410_INTMSK);
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submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
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/* check to see if we need to mask the parent IRQ */
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if ((submask & subcheck) == subcheck) {
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__raw_writel(mask | parentbit, S3C2410_INTMSK);
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}
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/* write back masks */
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__raw_writel(submask, S3C2410_INTSUBMSK);
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}
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static inline void
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s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit)
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{
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unsigned long mask;
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unsigned long submask;
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submask = __raw_readl(S3C2410_INTSUBMSK);
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mask = __raw_readl(S3C2410_INTMSK);
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submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
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mask &= ~parentbit;
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/* write back masks */
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__raw_writel(submask, S3C2410_INTSUBMSK);
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__raw_writel(mask, S3C2410_INTMSK);
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}
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static inline void
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s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group)
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{
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unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
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s3c_irqsub_mask(irqno, parentmask, group);
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__raw_writel(bit, S3C2410_SUBSRCPND);
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/* only ack parent if we've got all the irqs (seems we must
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* ack, all and hope that the irq system retriggers ok when
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* the interrupt goes off again)
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*/
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if (1) {
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__raw_writel(parentmask, S3C2410_SRCPND);
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__raw_writel(parentmask, S3C2410_INTPND);
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}
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}
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static inline void
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s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group)
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{
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unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
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__raw_writel(bit, S3C2410_SUBSRCPND);
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/* only ack parent if we've got all the irqs (seems we must
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* ack, all and hope that the irq system retriggers ok when
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* the interrupt goes off again)
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*/
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if (1) {
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__raw_writel(parentmask, S3C2410_SRCPND);
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__raw_writel(parentmask, S3C2410_INTPND);
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}
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}
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/* exported for use in arch/arm/mach-s3c2410 */
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extern int s3c_irq_wake(unsigned int irqno, unsigned int state);
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extern int s3c_irqext_type(unsigned int irq, unsigned int type);
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