mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-09-22 12:24:38 +00:00
e65fa9f59e
Neither of these have had any maintenance in years, and there's no interest in keeping them straggling along. These have already been slated for removal some time, so finally just get rid of them. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
169 lines
4.5 KiB
C
169 lines
4.5 KiB
C
#ifndef __ASM_SH_IRQ_H
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#define __ASM_SH_IRQ_H
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#include <asm/machvec.h>
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#include <asm/ptrace.h> /* for pt_regs */
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/* NR_IRQS is made from three components:
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* 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
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* 2. PINT_NR_IRQS - number of PINT interrupts
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* 3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
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*/
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/* 1. ONCHIP_NR_IRQS */
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#if defined(CONFIG_CPU_SUBTYPE_SH7604)
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# define ONCHIP_NR_IRQS 24 // Actually 21
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#elif defined(CONFIG_CPU_SUBTYPE_SH7707)
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# define ONCHIP_NR_IRQS 64
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# define PINT_NR_IRQS 16
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#elif defined(CONFIG_CPU_SUBTYPE_SH7708)
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# define ONCHIP_NR_IRQS 32
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#elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
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defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7705)
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# define ONCHIP_NR_IRQS 64 // Actually 61
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# define PINT_NR_IRQS 16
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#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
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# define ONCHIP_NR_IRQS 104
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#elif defined(CONFIG_CPU_SUBTYPE_SH7750)
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# define ONCHIP_NR_IRQS 48 // Actually 44
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#elif defined(CONFIG_CPU_SUBTYPE_SH7751)
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# define ONCHIP_NR_IRQS 72
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#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
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# define ONCHIP_NR_IRQS 112 /* XXX */
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#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
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# define ONCHIP_NR_IRQS 72
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#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
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# define ONCHIP_NR_IRQS 144
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#elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
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defined(CONFIG_CPU_SUBTYPE_SH73180) || \
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defined(CONFIG_CPU_SUBTYPE_SH7343) || \
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defined(CONFIG_CPU_SUBTYPE_SH7722)
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# define ONCHIP_NR_IRQS 109
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#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
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# define ONCHIP_NR_IRQS 111
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#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
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# define ONCHIP_NR_IRQS 256
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#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
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# define ONCHIP_NR_IRQS 128
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#elif defined(CONFIG_SH_UNKNOWN) /* Most be last */
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# define ONCHIP_NR_IRQS 144
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#endif
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/* 2. PINT_NR_IRQS */
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#ifdef CONFIG_SH_UNKNOWN
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# define PINT_NR_IRQS 16
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#else
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# ifndef PINT_NR_IRQS
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# define PINT_NR_IRQS 0
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# endif
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#endif
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#if PINT_NR_IRQS > 0
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# define PINT_IRQ_BASE ONCHIP_NR_IRQS
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#endif
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/* 3. OFFCHIP_NR_IRQS */
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#if defined(CONFIG_HD64461)
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# define OFFCHIP_NR_IRQS 18
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#elif defined(CONFIG_HD64465)
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# define OFFCHIP_NR_IRQS 16
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#elif defined (CONFIG_SH_DREAMCAST)
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# define OFFCHIP_NR_IRQS 96
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#elif defined (CONFIG_SH_TITAN)
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# define OFFCHIP_NR_IRQS 4
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#elif defined(CONFIG_SH_R7780RP)
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# define OFFCHIP_NR_IRQS 16
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#elif defined(CONFIG_SH_7343_SOLUTION_ENGINE)
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# define OFFCHIP_NR_IRQS 12
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#elif defined(CONFIG_SH_7722_SOLUTION_ENGINE)
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# define OFFCHIP_NR_IRQS 14
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#elif defined(CONFIG_SH_UNKNOWN)
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# define OFFCHIP_NR_IRQS 16 /* Must also be last */
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#else
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# define OFFCHIP_NR_IRQS 0
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#endif
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#if OFFCHIP_NR_IRQS > 0
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# define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
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#endif
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/* NR_IRQS. 1+2+3 */
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#define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
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/*
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* Convert back and forth between INTEVT and IRQ values.
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*/
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#define evt2irq(evt) (((evt) >> 5) - 16)
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#define irq2evt(irq) (((irq) + 16) << 5)
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/*
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* Simple Mask Register Support
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*/
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extern void make_maskreg_irq(unsigned int irq);
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extern unsigned short *irq_mask_register;
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/*
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* PINT IRQs
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*/
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void init_IRQ_pint(void);
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/*
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* The shift value is now the number of bits to shift, not the number of
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* bits/4. This is to make it easier to read the value directly from the
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* datasheets. The IPR address, addr, will be set from ipr_idx via the
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* map_ipridx_to_addr function.
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*/
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struct ipr_data {
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unsigned int irq;
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int ipr_idx; /* Index for the IPR registered */
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int shift; /* Number of bits to shift the data */
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int priority; /* The priority */
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unsigned int addr; /* Address of Interrupt Priority Register */
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};
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/*
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* Given an IPR IDX, map the value to an IPR register address.
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*/
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unsigned int map_ipridx_to_addr(int idx);
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/*
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* Enable individual interrupt mode for external IPR IRQs.
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*/
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void ipr_irq_enable_irlm(void);
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/*
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* Function for "on chip support modules".
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*/
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void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
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void make_imask_irq(unsigned int irq);
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void init_IRQ_ipr(void);
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struct intc2_data {
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unsigned short irq;
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unsigned char ipr_offset, ipr_shift;
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unsigned char msk_offset, msk_shift;
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unsigned char priority;
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};
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void make_intc2_irq(struct intc2_data *, unsigned int nr_irqs);
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void init_IRQ_intc2(void);
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static inline int generic_irq_demux(int irq)
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{
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return irq;
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}
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#define irq_canonicalize(irq) (irq)
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#define irq_demux(irq) sh_mv.mv_irq_demux(irq)
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#ifdef CONFIG_4KSTACKS
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extern void irq_ctx_init(int cpu);
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extern void irq_ctx_exit(int cpu);
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# define __ARCH_HAS_DO_SOFTIRQ
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#else
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# define irq_ctx_init(cpu) do { } while (0)
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# define irq_ctx_exit(cpu) do { } while (0)
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#endif
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#endif /* __ASM_SH_IRQ_H */
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