mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-09-22 04:15:02 +00:00
2b431ff74a
This patch increases reset delay from 50 usec to 80 usec for USB HOST PHY. In order to reset USB HOST PHY controller properly, a little extra time is required during its reset cycle. Signed-off-by: Yulgon Kim <yulgon.kim@samsung.com> Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
136 lines
3 KiB
C
136 lines
3 KiB
C
/*
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* Copyright (C) 2011 Samsung Electronics Co.Ltd
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* Author: Joonyoung Shim <jy0922.shim@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <mach/regs-pmu.h>
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#include <mach/regs-usb-phy.h>
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#include <plat/cpu.h>
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#include <plat/usb-phy.h>
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static int exynos4_usb_phy1_init(struct platform_device *pdev)
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{
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struct clk *otg_clk;
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struct clk *xusbxti_clk;
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u32 phyclk;
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u32 rstcon;
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int err;
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otg_clk = clk_get(&pdev->dev, "otg");
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if (IS_ERR(otg_clk)) {
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dev_err(&pdev->dev, "Failed to get otg clock\n");
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return PTR_ERR(otg_clk);
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}
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err = clk_enable(otg_clk);
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if (err) {
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clk_put(otg_clk);
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return err;
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}
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writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE,
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S5P_USBHOST_PHY_CONTROL);
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/* set clock frequency for PLL */
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phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK;
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xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
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if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
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switch (clk_get_rate(xusbxti_clk)) {
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case 12 * MHZ:
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phyclk |= CLKSEL_12M;
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break;
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case 24 * MHZ:
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phyclk |= CLKSEL_24M;
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break;
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default:
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case 48 * MHZ:
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/* default reference clock */
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break;
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}
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clk_put(xusbxti_clk);
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}
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writel(phyclk, EXYNOS4_PHYCLK);
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/* floating prevention logic: disable */
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writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
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/* set to normal HSIC 0 and 1 of PHY1 */
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writel((readl(EXYNOS4_PHYPWR) & ~PHY1_HSIC_NORMAL_MASK),
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EXYNOS4_PHYPWR);
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/* set to normal standard USB of PHY1 */
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writel((readl(EXYNOS4_PHYPWR) & ~PHY1_STD_NORMAL_MASK), EXYNOS4_PHYPWR);
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/* reset all ports of both PHY and Link */
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rstcon = readl(EXYNOS4_RSTCON) | HOST_LINK_PORT_SWRST_MASK |
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PHY1_SWRST_MASK;
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writel(rstcon, EXYNOS4_RSTCON);
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udelay(10);
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rstcon &= ~(HOST_LINK_PORT_SWRST_MASK | PHY1_SWRST_MASK);
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writel(rstcon, EXYNOS4_RSTCON);
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udelay(80);
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clk_disable(otg_clk);
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clk_put(otg_clk);
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return 0;
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}
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static int exynos4_usb_phy1_exit(struct platform_device *pdev)
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{
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struct clk *otg_clk;
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int err;
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otg_clk = clk_get(&pdev->dev, "otg");
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if (IS_ERR(otg_clk)) {
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dev_err(&pdev->dev, "Failed to get otg clock\n");
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return PTR_ERR(otg_clk);
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}
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err = clk_enable(otg_clk);
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if (err) {
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clk_put(otg_clk);
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return err;
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}
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writel((readl(EXYNOS4_PHYPWR) | PHY1_STD_ANALOG_POWERDOWN),
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EXYNOS4_PHYPWR);
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writel(readl(S5P_USBHOST_PHY_CONTROL) & ~S5P_USBHOST_PHY_ENABLE,
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S5P_USBHOST_PHY_CONTROL);
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clk_disable(otg_clk);
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clk_put(otg_clk);
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return 0;
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}
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int s5p_usb_phy_init(struct platform_device *pdev, int type)
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{
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if (type == S5P_USB_PHY_HOST)
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return exynos4_usb_phy1_init(pdev);
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return -EINVAL;
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}
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int s5p_usb_phy_exit(struct platform_device *pdev, int type)
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{
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if (type == S5P_USB_PHY_HOST)
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return exynos4_usb_phy1_exit(pdev);
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return -EINVAL;
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}
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