mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-09-22 04:15:02 +00:00
0ea1293009
Rather than checking the MMU status in every instance of addruart, do it once in kernel/debug.S, and change the existing addruart macros to return both physical and virtual addresses. The main debug code can then select the appropriate address to use. This will also allow us to retreive the address of a uart for the MMU state that we're not current in. Updated with fixes for OMAP from Jason Wang <jason77.wang@gmail.com> and Tony Lindgren <tony@atomide.com>, and fix for versatile express from Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>. Signed-off-by: Jeremy Kerr <jeremy.kerr@canonical.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Jason Wang <jason77.wang@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Tested-by: Kevin Hilman <khilman@deeprootsystems.com>
62 lines
1.5 KiB
ArmAsm
62 lines
1.5 KiB
ArmAsm
/* arch/arm/mach-sa1100/include/mach/debug-macro.S
|
|
*
|
|
* Debugging macro include header
|
|
*
|
|
* Copyright (C) 1994-1999 Russell King
|
|
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
*/
|
|
#include <mach/hardware.h>
|
|
|
|
.macro addruart, rp, rv
|
|
mrc p15, 0, \rp, c1, c0
|
|
tst \rp, #1 @ MMU enabled?
|
|
moveq \rp, #0x80000000 @ physical base address
|
|
movne \rp, #0xf8000000 @ virtual address
|
|
|
|
@ We probe for the active serial port here, coherently with
|
|
@ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h.
|
|
@ We assume r1 can be clobbered.
|
|
|
|
@ see if Ser3 is active
|
|
add \rp, \rp, #0x00050000
|
|
ldr \rv, [\rp, #UTCR3]
|
|
tst \rv, #UTCR3_TXE
|
|
|
|
@ if Ser3 is inactive, then try Ser1
|
|
addeq \rp, \rp, #(0x00010000 - 0x00050000)
|
|
ldreq \rv, [\rp, #UTCR3]
|
|
tsteq \rv, #UTCR3_TXE
|
|
|
|
@ if Ser1 is inactive, then try Ser2
|
|
addeq \rp, \rp, #(0x00030000 - 0x00010000)
|
|
ldreq \rv, [\rp, #UTCR3]
|
|
tsteq \rv, #UTCR3_TXE
|
|
|
|
@ clear top bits, and generate both phys and virt addresses
|
|
lsl \rp, \rp, #8
|
|
lsr \rp, \rp, #8
|
|
orr \rv, \rp, #0xf8000000 @ virtual
|
|
orr \rp, \rp, #0x80000000 @ physical
|
|
|
|
.endm
|
|
|
|
.macro senduart,rd,rx
|
|
str \rd, [\rx, #UTDR]
|
|
.endm
|
|
|
|
.macro waituart,rd,rx
|
|
1001: ldr \rd, [\rx, #UTSR1]
|
|
tst \rd, #UTSR1_TNF
|
|
beq 1001b
|
|
.endm
|
|
|
|
.macro busyuart,rd,rx
|
|
1001: ldr \rd, [\rx, #UTSR1]
|
|
tst \rd, #UTSR1_TBY
|
|
bne 1001b
|
|
.endm
|