mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-10-08 12:43:22 +00:00
a0776ec8e9
It's not efficient to use a per-cpu variable just to store
how many physical stack register a cpu has. Ever since the
incarnation of ia64 up till upcoming Montecito processor, that
variable has "glued" to 96. Having a variable in memory means
that the kernel is burning an extra cacheline access on every
syscall and kernel exit path. Such "static" value is better
served with the instruction patching utility exists today.
Convert ia64_phys_stacked_size_p8 into dynamic insn patching.
This also has a pleasant side effect of eliminating access to
per-cpu area while psr.ic=0 in the kernel exit path. (fixable
for per-cpu DTC work, but why bother?)
There are some concerns with the default value that the instruc-
tion encoded in the kernel image. It shouldn't be concerned.
The reasons are:
(1) cpu_init() is called at CPU initialization. In there, we
find out physical stack register size from PAL and patch
two instructions in kernel exit code. The code in question
can not be executed before the patching is done.
(2) current implementation stores zero in ia64_phys_stacked_size_p8,
and that's what the current kernel exit path loads the value with.
With the new code, it is equivalent that we store reg size 96
in ia64_phys_stacked_size_p8, thus creating a better safety net.
Given (1) above can never fail, having (2) is just a bonus.
All in all, this patch allow one less memory reference in the kernel
exit path, thus reducing syscall and interrupt return latency; and
avoid polluting potential useful data in the CPU cache.
Signed-off-by: Ken Chen <kenneth.w.chen@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
274 lines
6.7 KiB
ArmAsm
274 lines
6.7 KiB
ArmAsm
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#include <asm/cache.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#define LOAD_OFFSET (KERNEL_START - KERNEL_TR_PAGE_SIZE)
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#include <asm-generic/vmlinux.lds.h>
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#define IVT_TEXT \
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VMLINUX_SYMBOL(__start_ivt_text) = .; \
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*(.text.ivt) \
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VMLINUX_SYMBOL(__end_ivt_text) = .;
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OUTPUT_FORMAT("elf64-ia64-little")
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OUTPUT_ARCH(ia64)
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ENTRY(phys_start)
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jiffies = jiffies_64;
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PHDRS {
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code PT_LOAD;
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percpu PT_LOAD;
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data PT_LOAD;
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}
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SECTIONS
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{
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/* Sections to be discarded */
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/DISCARD/ : {
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*(.exit.text)
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*(.exit.data)
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*(.exitcall.exit)
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*(.IA_64.unwind.exit.text)
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*(.IA_64.unwind_info.exit.text)
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}
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v = PAGE_OFFSET; /* this symbol is here to make debugging easier... */
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phys_start = _start - LOAD_OFFSET;
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code : { } :code
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. = KERNEL_START;
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_text = .;
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_stext = .;
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.text : AT(ADDR(.text) - LOAD_OFFSET)
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{
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IVT_TEXT
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*(.text)
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SCHED_TEXT
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LOCK_TEXT
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KPROBES_TEXT
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*(.gnu.linkonce.t*)
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}
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.text2 : AT(ADDR(.text2) - LOAD_OFFSET)
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{ *(.text2) }
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#ifdef CONFIG_SMP
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.text.lock : AT(ADDR(.text.lock) - LOAD_OFFSET)
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{ *(.text.lock) }
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#endif
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_etext = .;
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/* Read-only data */
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/* Exception table */
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. = ALIGN(16);
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__ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET)
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{
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__start___ex_table = .;
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*(__ex_table)
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__stop___ex_table = .;
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}
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/* MCA table */
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. = ALIGN(16);
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__mca_table : AT(ADDR(__mca_table) - LOAD_OFFSET)
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{
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__start___mca_table = .;
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*(__mca_table)
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__stop___mca_table = .;
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}
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.data.patch.phys_stack_reg : AT(ADDR(.data.patch.phys_stack_reg) - LOAD_OFFSET)
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{
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__start___phys_stack_reg_patchlist = .;
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*(.data.patch.phys_stack_reg)
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__end___phys_stack_reg_patchlist = .;
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}
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/* Global data */
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_data = .;
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/* Unwind info & table: */
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. = ALIGN(8);
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.IA_64.unwind_info : AT(ADDR(.IA_64.unwind_info) - LOAD_OFFSET)
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{ *(.IA_64.unwind_info*) }
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.IA_64.unwind : AT(ADDR(.IA_64.unwind) - LOAD_OFFSET)
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{
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__start_unwind = .;
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*(.IA_64.unwind*)
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__end_unwind = .;
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}
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RODATA
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.opd : AT(ADDR(.opd) - LOAD_OFFSET)
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{ *(.opd) }
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/* Initialization code and data: */
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. = ALIGN(PAGE_SIZE);
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__init_begin = .;
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.init.text : AT(ADDR(.init.text) - LOAD_OFFSET)
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{
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_sinittext = .;
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*(.init.text)
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_einittext = .;
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}
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.init.data : AT(ADDR(.init.data) - LOAD_OFFSET)
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{ *(.init.data) }
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.init.ramfs : AT(ADDR(.init.ramfs) - LOAD_OFFSET)
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{
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__initramfs_start = .;
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*(.init.ramfs)
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__initramfs_end = .;
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}
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. = ALIGN(16);
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.init.setup : AT(ADDR(.init.setup) - LOAD_OFFSET)
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{
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__setup_start = .;
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*(.init.setup)
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__setup_end = .;
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}
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.initcall.init : AT(ADDR(.initcall.init) - LOAD_OFFSET)
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{
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__initcall_start = .;
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INITCALLS
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__initcall_end = .;
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}
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.data.patch.vtop : AT(ADDR(.data.patch.vtop) - LOAD_OFFSET)
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{
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__start___vtop_patchlist = .;
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*(.data.patch.vtop)
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__end___vtop_patchlist = .;
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}
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.data.patch.mckinley_e9 : AT(ADDR(.data.patch.mckinley_e9) - LOAD_OFFSET)
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{
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__start___mckinley_e9_bundles = .;
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*(.data.patch.mckinley_e9)
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__end___mckinley_e9_bundles = .;
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}
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#if defined(CONFIG_IA64_GENERIC)
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/* Machine Vector */
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. = ALIGN(16);
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.machvec : AT(ADDR(.machvec) - LOAD_OFFSET)
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{
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machvec_start = .;
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*(.machvec)
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machvec_end = .;
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}
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#endif
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__con_initcall_start = .;
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.con_initcall.init : AT(ADDR(.con_initcall.init) - LOAD_OFFSET)
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{ *(.con_initcall.init) }
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__con_initcall_end = .;
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__security_initcall_start = .;
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.security_initcall.init : AT(ADDR(.security_initcall.init) - LOAD_OFFSET)
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{ *(.security_initcall.init) }
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__security_initcall_end = .;
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. = ALIGN(PAGE_SIZE);
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__init_end = .;
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/* The initial task and kernel stack */
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.data.init_task : AT(ADDR(.data.init_task) - LOAD_OFFSET)
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{ *(.data.init_task) }
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.data.page_aligned : AT(ADDR(.data.page_aligned) - LOAD_OFFSET)
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{ *(__special_page_section)
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__start_gate_section = .;
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*(.data.gate)
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__stop_gate_section = .;
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}
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. = ALIGN(PAGE_SIZE); /* make sure the gate page doesn't expose
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* kernel data
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*/
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.data.read_mostly : AT(ADDR(.data.read_mostly) - LOAD_OFFSET)
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{ *(.data.read_mostly) }
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.data.cacheline_aligned : AT(ADDR(.data.cacheline_aligned) - LOAD_OFFSET)
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{ *(.data.cacheline_aligned) }
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/* Per-cpu data: */
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percpu : { } :percpu
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. = ALIGN(PERCPU_PAGE_SIZE);
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__phys_per_cpu_start = .;
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.data.percpu PERCPU_ADDR : AT(__phys_per_cpu_start - LOAD_OFFSET)
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{
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__per_cpu_start = .;
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*(.data.percpu)
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__per_cpu_end = .;
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}
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. = __phys_per_cpu_start + PERCPU_PAGE_SIZE; /* ensure percpu data fits
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* into percpu page size
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*/
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data : { } :data
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.data : AT(ADDR(.data) - LOAD_OFFSET)
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{ *(.data) *(.data1) *(.gnu.linkonce.d*) CONSTRUCTORS }
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. = ALIGN(16); /* gp must be 16-byte aligned for exc. table */
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.got : AT(ADDR(.got) - LOAD_OFFSET)
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{ *(.got.plt) *(.got) }
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__gp = ADDR(.got) + 0x200000;
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/* We want the small data sections together, so single-instruction offsets
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can access them all, and initialized data all before uninitialized, so
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we can shorten the on-disk segment size. */
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.sdata : AT(ADDR(.sdata) - LOAD_OFFSET)
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{ *(.sdata) *(.sdata1) *(.srdata) }
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_edata = .;
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_bss = .;
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.sbss : AT(ADDR(.sbss) - LOAD_OFFSET)
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{ *(.sbss) *(.scommon) }
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.bss : AT(ADDR(.bss) - LOAD_OFFSET)
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{ *(.bss) *(COMMON) }
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_end = .;
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code : { } :code
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/* Stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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/* DWARF debug sections.
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Symbols in the DWARF debugging sections are relative to the beginning
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of the section so we begin them at 0. */
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/* DWARF 1 */
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.debug 0 : { *(.debug) }
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.line 0 : { *(.line) }
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/* GNU DWARF 1 extensions */
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.debug_srcinfo 0 : { *(.debug_srcinfo) }
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.debug_sfnames 0 : { *(.debug_sfnames) }
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/* DWARF 1.1 and DWARF 2 */
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.debug_aranges 0 : { *(.debug_aranges) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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/* DWARF 2 */
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.debug_info 0 : { *(.debug_info) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_line 0 : { *(.debug_line) }
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.debug_frame 0 : { *(.debug_frame) }
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.debug_str 0 : { *(.debug_str) }
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.debug_loc 0 : { *(.debug_loc) }
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.debug_macinfo 0 : { *(.debug_macinfo) }
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/* SGI/MIPS DWARF 2 extensions */
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.debug_weaknames 0 : { *(.debug_weaknames) }
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.debug_funcnames 0 : { *(.debug_funcnames) }
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.debug_typenames 0 : { *(.debug_typenames) }
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.debug_varnames 0 : { *(.debug_varnames) }
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/* These must appear regardless of . */
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/* Discard them for now since Intel SoftSDV cannot handle them.
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.comment 0 : { *(.comment) }
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.note 0 : { *(.note) }
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*/
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/DISCARD/ : { *(.comment) }
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/DISCARD/ : { *(.note) }
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}
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