472 lines
10 KiB
Plaintext
472 lines
10 KiB
Plaintext
/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "skeleton64.dtsi"
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#include <dt-bindings/clock/msm-clocks-8936.h>
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#include <dt-bindings/clock/msm-cpu-clocks-8939.h>
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#include "msm8939-common.dtsi"
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#include "msm8939-coresight.dtsi"
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#include "msm8939-cpu.dtsi"
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#include "msm8939-v3.0-pm.dtsi"
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#include "msm8939-smem.dtsi"
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#include "msm8939-smp2p.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. MSM8939v3.0";
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compatible = "qcom,msm8939";
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qcom,msm-id = <239 0x30000>, <241 0x30000>, <263 0x30000>;
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chosen {
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bootargs = "boot_cpus=0,4,5,6,7 sched_enable_hmp=1";
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};
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};
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&soc {
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 2 0xff08>,
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<1 3 0xff08>,
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<1 4 0xff08>,
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<1 1 0xff08>;
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clock-frequency = <19200000>;
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};
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clock_cpu: qcom,cpu-clock-8939@b111050 {
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compatible = "qcom,cpu-clock-8939";
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reg = <0xb111050 0x8>,
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<0xb011050 0x8>,
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<0xb1d1050 0x8>,
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<0x5800c 0x8>,
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<0x58000 0x8>,
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<0x58004 0x8>;
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reg-names = "apcs-c0-rcg-base", "apcs-c1-rcg-base",
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"apcs-cci-rcg-base", "efuse", "efuse1",
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"efuse2";
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vdd-c0-supply = <&apc_vreg_corner>;
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vdd-c1-supply = <&apc_vreg_corner>;
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vdd-cci-supply = <&apc_vreg_corner>;
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clocks = <&clock_gcc clk_gpll0_ao>,
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<&clock_gcc clk_a53ss_c0_pll>,
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<&clock_gcc clk_gpll0_ao>,
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<&clock_gcc clk_a53ss_c1_pll>,
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<&clock_gcc clk_gpll0_ao>,
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<&clock_gcc clk_a53ss_cci_pll>;
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clock-names = "clk-c0-4", "clk-c0-5",
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"clk-c1-4", "clk-c1-5",
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"clk-cci-4", "clk-cci-5";
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qcom,speed0-bin-v0-c0 =
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< 0 0>,
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< 250000000 3>,
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< 500000000 9>,
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< 800000000 12>,
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< 998400000 17>,
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< 1209600000 24>;
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qcom,speed0-bin-v0-c1 =
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< 0 0>,
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< 400000000 3>,
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< 800000000 9>,
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< 960000000 12>,
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< 1209600000 14>,
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< 1344000000 17>;
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qcom,speed0-bin-v0-cci =
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< 0 0>,
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< 200000000 3>,
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< 300000000 11>,
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< 400000000 15>,
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< 600000000 17>;
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qcom,speed2-bin-v0-c0 =
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< 0 0>,
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< 250000000 3>,
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< 500000000 9>,
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< 800000000 12>,
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< 998400000 17>,
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< 1209600000 24>;
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qcom,speed2-bin-v0-c1 =
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< 0 0>,
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< 400000000 3>,
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< 800000000 9>,
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< 960000000 12>,
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< 1209600000 14>,
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< 1344000000 17>,
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< 1459200000 20>,
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< 1497600000 21>;
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qcom,speed2-bin-v0-cci =
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< 0 0>,
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< 200000000 3>,
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< 300000000 11>,
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< 400000000 15>,
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< 600000000 17>;
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qcom,speed2-bin-v2-c0 =
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< 0 0>,
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< 250000000 3>,
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< 500000000 9>,
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< 800000000 12>,
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< 998400000 17>,
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< 1209600000 24>;
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qcom,speed2-bin-v2-c1 =
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< 0 0>,
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< 400000000 3>,
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< 800000000 9>,
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< 960000000 12>,
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< 1344000000 17>,
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< 1459200000 20>;
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qcom,speed2-bin-v2-cci =
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< 0 0>,
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< 200000000 3>,
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< 300000000 11>,
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< 400000000 15>,
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< 600000000 17>;
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qcom,speed4-bin-v0-c0 =
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< 0 0>,
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< 250000000 3>,
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< 500000000 9>,
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< 800000000 12>,
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< 998400000 17>,
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< 1209600000 24>;
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qcom,speed4-bin-v0-c1 =
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< 0 0>,
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< 400000000 3>,
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< 800000000 9>,
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< 960000000 12>,
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< 1209600000 14>,
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< 1344000000 17>,
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< 1459200000 20>,
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< 1497600000 21>,
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< 1651200000 26>;
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qcom,speed4-bin-v0-cci =
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< 0 0>,
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< 200000000 3>,
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< 300000000 11>,
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< 400000000 15>,
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< 600000000 17>;
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qcom,speed5-bin-v0-c0 =
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< 0 0>,
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< 250000000 3>,
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< 500000000 9>,
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< 800000000 12>,
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< 998400000 17>,
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< 1209600000 24>;
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qcom,speed5-bin-v0-c1 =
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< 0 0>,
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< 400000000 3>,
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< 800000000 9>,
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< 960000000 12>,
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< 1209600000 14>,
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< 1344000000 17>,
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< 1459200000 20>,
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< 1497600000 21>,
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< 1651200000 26>;
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qcom,speed5-bin-v0-cci =
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< 0 0>,
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< 200000000 3>,
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< 300000000 11>,
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< 400000000 15>,
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< 600000000 17>;
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qcom,speed5-bin-v6-c0 =
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< 0 0>,
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< 250000000 3>,
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< 500000000 9>,
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< 800000000 12>,
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< 998400000 17>,
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< 1209600000 24>;
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qcom,speed5-bin-v6-c1 =
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< 0 0>,
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< 400000000 3>,
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< 800000000 9>,
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< 960000000 12>,
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< 1209600000 14>,
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< 1344000000 17>,
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< 1459200000 20>,
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< 1497600000 21>,
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< 1651200000 26>;
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qcom,speed5-bin-v6-cci =
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< 0 0>,
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< 200000000 3>,
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< 300000000 11>,
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< 400000000 15>,
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< 600000000 17>;
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#clock-cells = <1>;
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};
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cci_cache: qcom,cci {
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compatible = "devfreq-simple-dev";
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clock-names = "devfreq_clk";
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clocks = <&clock_cpu clk_a53ssmux_cci>;
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governor = "cpufreq";
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freq-tbl-khz =
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< 200000 >,
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< 297600 >,
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< 400000 >,
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< 595200 >;
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};
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cpubw: qcom,cpubw {
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compatible = "qcom,devbw";
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governor = "cpufreq";
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qcom,src-dst-ports = <1 512>;
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qcom,active-only;
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qcom,bw-tbl =
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< 1525 /* 100 MHz */ >,
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< 2636 /* 172.8 MHz */ >,
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< 3955 /* 259.2 MHz */ >,
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< 5346 /* 350.4 MHz */ >,
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< 5712 /* 374.4 MHz */ >,
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< 6079 /* 398.4 MHz */ >;
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};
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devfreq-cpufreq {
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cpubw-cpufreq {
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target-dev = <&cpubw>;
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cpu-to-dev-map-0 =
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< 200000 1525 >,
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< 800000 2636 >,
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< 1209600 5346 >,
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< 1651200 6079 >;
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cpu-to-dev-map-4 =
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< 200000 1525 >,
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< 499200 2636 >,
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< 800000 5346 >,
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< 1209600 6079 >;
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};
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cci-cpufreq {
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target-dev = <&cci_cache>;
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cpu-to-dev-map-0 =
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< 200000 200000 >,
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< 400000 200000 >,
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< 1209600 297000 >,
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< 1651200 595200 >;
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cpu-to-dev-map-4 =
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< 200000 200000 >,
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< 249600 200000 >,
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< 800000 297600 >,
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< 1209600 595200 >;
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};
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};
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qcom,msm-cpufreq {
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compatible = "qcom,msm-cpufreq";
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clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk",
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"cpu3_clk", "cpu4_clk", "cpu5_clk",
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"cpu6_clk", "cpu7_clk";
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clocks = <&clock_cpu clk_a53ssmux_cci>,
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<&clock_cpu clk_a53ssmux_bc>,
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<&clock_cpu clk_a53ssmux_bc>,
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<&clock_cpu clk_a53ssmux_bc>,
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<&clock_cpu clk_a53ssmux_bc>,
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<&clock_cpu clk_a53ssmux_lc>,
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<&clock_cpu clk_a53ssmux_lc>,
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<&clock_cpu clk_a53ssmux_lc>,
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<&clock_cpu clk_a53ssmux_lc>;
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qcom,governor-per-policy;
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qcom,cpufreq-table-0 =
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< 200000 >,
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< 345600 >,
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< 400000 >,
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< 533330 >,
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< 800000 >,
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< 960000 >,
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< 1209600 >,
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< 1344000 >,
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< 1459200 >,
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< 1497600 >,
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< 1612800 >,
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< 1651200 >;
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qcom,cpufreq-table-4 =
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< 200000 >,
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< 249600 >,
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< 499200 >,
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< 800000 >,
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< 998400 >,
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< 1209600 >;
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};
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cpu-pmu {
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compatible = "arm,armv8-pmuv3";
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qcom,irq-is-percpu;
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interrupts = <1 7 0xff00>;
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};
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jtag_fuse: jtagfuse@5e01c {
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compatible = "qcom,jtag-fuse-v2";
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reg = <0x5e01c 0x8>;
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reg-names = "fuse-base";
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};
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jtag_mm0: jtagmm@8fc000 {
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compatible = "qcom,jtagv8-mm";
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reg = <0x8fc000 0x1000>,
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<0x8f0000 0x1000>;
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reg-names = "etm-base", "debug-base";
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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qcom,coresight-jtagmm-cpu = <&CPU0>;
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};
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jtag_mm1: jtagmm@8fd000 {
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compatible = "qcom,jtagv8-mm";
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reg = <0x8fd000 0x1000>,
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<0x8f2000 0x1000>;
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reg-names = "etm-base", "debug-base";
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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qcom,coresight-jtagmm-cpu = <&CPU1>;
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};
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jtag_mm2: jtagmm@8fe000 {
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compatible = "qcom,jtagv8-mm";
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reg = <0x8fe000 0x1000>,
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<0x8f4000 0x1000>;
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reg-names = "etm-base", "debug-base";
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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qcom,coresight-jtagmm-cpu = <&CPU2>;
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};
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jtag_mm3: jtagmm@8ff000 {
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compatible = "qcom,jtagv8-mm";
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reg = <0x8ff000 0x1000>,
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<0x8f6000 0x1000>;
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reg-names = "etm-base", "debug-base";
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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qcom,coresight-jtagmm-cpu = <&CPU3>;
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};
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jtag_mm4: jtagmm@8dc000 {
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compatible = "qcom,jtagv8-mm";
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reg = <0x8dc000 0x1000>,
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<0x8d0000 0x1000>;
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reg-names = "etm-base", "debug-base";
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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qcom,coresight-jtagmm-cpu = <&CPU4>;
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};
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jtag_mm5: jtagmm@8dd000 {
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compatible = "qcom,jtagv8-mm";
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reg = <0x8dd000 0x1000>,
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<0x8d2000 0x1000>;
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reg-names = "etm-base", "debug-base";
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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qcom,coresight-jtagmm-cpu = <&CPU5>;
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};
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jtag_mm6: jtagmm@8de000 {
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compatible = "qcom,jtagv8-mm";
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reg = <0x8de000 0x1000>,
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<0x8d4000 0x1000>;
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reg-names = "etm-base", "debug-base";
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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qcom,coresight-jtagmm-cpu = <&CPU6>;
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};
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jtag_mm7: jtagmm@8df000 {
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compatible = "qcom,jtagv8-mm";
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reg = <0x8df000 0x1000>,
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<0x8d6000 0x1000>;
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reg-names = "etm-base", "debug-base";
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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qcom,coresight-jtagmm-cpu = <&CPU7>;
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};
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qcom,msm-thermal {
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qcom,freq-control-list = <&CPU0 &CPU1 &CPU2 &CPU3
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&CPU4 &CPU5 &CPU6 &CPU7>;
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qcom,core-control-list = <&CPU0 &CPU1 &CPU2 &CPU3
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&CPU4 &CPU5 &CPU6 &CPU7>;
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qcom,freq-mitigation-control-list = <&CPU0 &CPU1 &CPU2 &CPU3
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&CPU4 &CPU5 &CPU6 &CPU7>;
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};
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};
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&tsens {
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qcom,sensors = <10>;
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qcom,slope = <2911 2789 2906 2763 2922 2867 2833 2838 2840 2852>;
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qcom,sensor-id = <0 1 2 3 5 6 7 8 9 10>;
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};
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&bam_dmux {
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qcom,no-cpu-affinity;
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};
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&mdss_dsi0 {
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qcom,platform-regulator-settings = [03 08 07 00 20 07 01];
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/delete-node/ qcom,regulator-ldo-mode;
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};
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&mdss_dsi1 {
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qcom,platform-regulator-settings = [03 08 07 00 20 07 01];
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/delete-node/ qcom,regulator-ldo-mode;
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};
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&clock_gcc {
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compatible = "qcom,gcc-8936-v3";
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};
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&gdsc_oxili_gx {
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clock-names = "core_root_clk", "gmem_clk";
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clocks = <&clock_gcc clk_gfx3d_clk_src>,
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<&clock_gcc clk_gcc_oxili_gmem_gate_clk>;
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qcom,enable-root-clk;
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status = "okay";
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};
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