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When there is a PCI-X mode 2 capable device behind the HT<->PCI-X bridge, the pci core decides that the device has the extended 4K config space, even though the bus is not operating in mode 2. This is because the u3_ht pci ops silently accept offsets greater than 255 but use only the 8 least significant bits, which means reading at offset 0x100 gets the data at offset 0x0, and causes confusion for lspci. Reject accesses to configuration space offsets greater than 255. Signed-off-by: Nathan Lynch <ntl@pobox.com> Signed-off-by: Paul Mackerras <paulus@samba.org> |
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boot | ||
configs | ||
kernel | ||
lib | ||
math-emu | ||
mm | ||
oprofile | ||
platforms | ||
sysdev | ||
xmon | ||
Kconfig | ||
Kconfig.debug | ||
Makefile |