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b45d527974
This is a driver for the SB1250 DUART, a dual serial port implementation included in the Broadcom family of SOCs descending from the SiByte SB1250 MIPS64 chip multiprocessor. It is a new implementation replacing the old-fashioned driver currently present in the linux-mips.org tree. It supports all the usual features one would expect from a(n asynchronous) serial driver, including modem line control (as far as hardware supports it -- there is edge detection logic missing from the DCD and RI lines and the driver does not implement polling of these lines at the moment), the serial console, BREAK transmission and reception, including the magic SysRq. The receive FIFO threshold is not maintained though. The driver was tested with a SWARM board which uses a BCM1250 SOC (which is dual MIPS64 CMP) and has both ports of the single DUART implemented wired externally. Both were tested. Testing included using the ports as terminal lines at 1200bps (which is the ports minimum), 115200bps and a couple of random speeds inbetween. The modem lines were verified to operate correctly. No testing was performed with a use as a network interface, like with SLIP or PPP. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
362 lines
13 KiB
C
362 lines
13 KiB
C
/* *********************************************************************
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* SB1250 Board Support Package
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*
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* UART Constants File: sb1250_uart.h
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*
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* This module contains constants and macros useful for
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* manipulating the SB1250's UARTs
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*
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* SB1250 specification level: User's manual 1/02/02
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*
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*********************************************************************
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*
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* Copyright 2000,2001,2002,2003
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* Broadcom Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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********************************************************************* */
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#ifndef _SB1250_UART_H
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#define _SB1250_UART_H
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#include "sb1250_defs.h"
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/* **********************************************************************
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* DUART Registers
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********************************************************************** */
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/*
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* DUART Mode Register #1 (Table 10-3)
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* Register: DUART_MODE_REG_1_A
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* Register: DUART_MODE_REG_1_B
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*/
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#define S_DUART_BITS_PER_CHAR 0
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#define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2,S_DUART_BITS_PER_CHAR)
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#define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x,S_DUART_BITS_PER_CHAR)
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#define K_DUART_BITS_PER_CHAR_RSV0 0
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#define K_DUART_BITS_PER_CHAR_RSV1 1
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#define K_DUART_BITS_PER_CHAR_7 2
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#define K_DUART_BITS_PER_CHAR_8 3
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#define V_DUART_BITS_PER_CHAR_RSV0 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0)
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#define V_DUART_BITS_PER_CHAR_RSV1 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1)
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#define V_DUART_BITS_PER_CHAR_7 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7)
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#define V_DUART_BITS_PER_CHAR_8 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8)
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#define M_DUART_PARITY_TYPE_EVEN 0x00
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#define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2)
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#define S_DUART_PARITY_MODE 3
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#define M_DUART_PARITY_MODE _SB_MAKEMASK(2,S_DUART_PARITY_MODE)
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#define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x,S_DUART_PARITY_MODE)
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#define K_DUART_PARITY_MODE_ADD 0
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#define K_DUART_PARITY_MODE_ADD_FIXED 1
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#define K_DUART_PARITY_MODE_NONE 2
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#define V_DUART_PARITY_MODE_ADD V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD)
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#define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED)
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#define V_DUART_PARITY_MODE_NONE V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE)
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#define M_DUART_TX_IRQ_SEL_TXRDY 0
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#define M_DUART_TX_IRQ_SEL_TXEMPT _SB_MAKEMASK1(5)
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#define M_DUART_RX_IRQ_SEL_RXRDY 0
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#define M_DUART_RX_IRQ_SEL_RXFULL _SB_MAKEMASK1(6)
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#define M_DUART_RX_RTS_ENA _SB_MAKEMASK1(7)
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/*
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* DUART Mode Register #2 (Table 10-4)
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* Register: DUART_MODE_REG_2_A
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* Register: DUART_MODE_REG_2_B
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*/
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#define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3,0) /* ignored */
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#define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3)
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#define M_DUART_STOP_BIT_LEN_1 0
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#define M_DUART_TX_CTS_ENA _SB_MAKEMASK1(4)
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#define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */
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#define S_DUART_CHAN_MODE 6
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#define M_DUART_CHAN_MODE _SB_MAKEMASK(2,S_DUART_CHAN_MODE)
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#define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x,S_DUART_CHAN_MODE)
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#define K_DUART_CHAN_MODE_NORMAL 0
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#define K_DUART_CHAN_MODE_LCL_LOOP 2
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#define K_DUART_CHAN_MODE_REM_LOOP 3
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#define V_DUART_CHAN_MODE_NORMAL V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_NORMAL)
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#define V_DUART_CHAN_MODE_LCL_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_LCL_LOOP)
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#define V_DUART_CHAN_MODE_REM_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_REM_LOOP)
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/*
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* DUART Command Register (Table 10-5)
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* Register: DUART_CMD_A
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* Register: DUART_CMD_B
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*/
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#define M_DUART_RX_EN _SB_MAKEMASK1(0)
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#define M_DUART_RX_DIS _SB_MAKEMASK1(1)
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#define M_DUART_TX_EN _SB_MAKEMASK1(2)
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#define M_DUART_TX_DIS _SB_MAKEMASK1(3)
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#define S_DUART_MISC_CMD 4
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#define M_DUART_MISC_CMD _SB_MAKEMASK(3,S_DUART_MISC_CMD)
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#define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x,S_DUART_MISC_CMD)
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#define K_DUART_MISC_CMD_NOACTION0 0
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#define K_DUART_MISC_CMD_NOACTION1 1
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#define K_DUART_MISC_CMD_RESET_RX 2
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#define K_DUART_MISC_CMD_RESET_TX 3
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#define K_DUART_MISC_CMD_NOACTION4 4
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#define K_DUART_MISC_CMD_RESET_BREAK_INT 5
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#define K_DUART_MISC_CMD_START_BREAK 6
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#define K_DUART_MISC_CMD_STOP_BREAK 7
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#define V_DUART_MISC_CMD_NOACTION0 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0)
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#define V_DUART_MISC_CMD_NOACTION1 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1)
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#define V_DUART_MISC_CMD_RESET_RX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX)
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#define V_DUART_MISC_CMD_RESET_TX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX)
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#define V_DUART_MISC_CMD_NOACTION4 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4)
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#define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT)
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#define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK)
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#define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK)
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#define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7)
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/*
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* DUART Status Register (Table 10-6)
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* Register: DUART_STATUS_A
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* Register: DUART_STATUS_B
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* READ-ONLY
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*/
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#define M_DUART_RX_RDY _SB_MAKEMASK1(0)
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#define M_DUART_RX_FFUL _SB_MAKEMASK1(1)
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#define M_DUART_TX_RDY _SB_MAKEMASK1(2)
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#define M_DUART_TX_EMT _SB_MAKEMASK1(3)
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#define M_DUART_OVRUN_ERR _SB_MAKEMASK1(4)
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#define M_DUART_PARITY_ERR _SB_MAKEMASK1(5)
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#define M_DUART_FRM_ERR _SB_MAKEMASK1(6)
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#define M_DUART_RCVD_BRK _SB_MAKEMASK1(7)
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/*
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* DUART Baud Rate Register (Table 10-7)
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* Register: DUART_CLK_SEL_A
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* Register: DUART_CLK_SEL_B
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*/
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#define M_DUART_CLK_COUNTER _SB_MAKEMASK(12,0)
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#define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1)
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/*
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* DUART Data Registers (Table 10-8 and 10-9)
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* Register: DUART_RX_HOLD_A
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* Register: DUART_RX_HOLD_B
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* Register: DUART_TX_HOLD_A
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* Register: DUART_TX_HOLD_B
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*/
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#define M_DUART_RX_DATA _SB_MAKEMASK(8,0)
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#define M_DUART_TX_DATA _SB_MAKEMASK(8,0)
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/*
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* DUART Input Port Register (Table 10-10)
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* Register: DUART_IN_PORT
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*/
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#define M_DUART_IN_PIN0_VAL _SB_MAKEMASK1(0)
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#define M_DUART_IN_PIN1_VAL _SB_MAKEMASK1(1)
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#define M_DUART_IN_PIN2_VAL _SB_MAKEMASK1(2)
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#define M_DUART_IN_PIN3_VAL _SB_MAKEMASK1(3)
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#define M_DUART_IN_PIN4_VAL _SB_MAKEMASK1(4)
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#define M_DUART_IN_PIN5_VAL _SB_MAKEMASK1(5)
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#define M_DUART_RIN0_PIN _SB_MAKEMASK1(6)
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#define M_DUART_RIN1_PIN _SB_MAKEMASK1(7)
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/*
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* DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13)
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* Register: DUART_INPORT_CHNG
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*/
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#define S_DUART_IN_PIN_VAL 0
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#define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4,S_DUART_IN_PIN_VAL)
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#define S_DUART_IN_PIN_CHNG 4
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#define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4,S_DUART_IN_PIN_CHNG)
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/*
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* DUART Output port control register (Table 10-14)
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* Register: DUART_OPCR
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*/
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#define M_DUART_OPCR_RESERVED0 _SB_MAKEMASK1(0) /* must be zero */
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#define M_DUART_OPC2_SEL _SB_MAKEMASK1(1)
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#define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */
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#define M_DUART_OPC3_SEL _SB_MAKEMASK1(3)
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#define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4,4) /* must be zero */
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/*
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* DUART Aux Control Register (Table 10-15)
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* Register: DUART_AUX_CTRL
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*/
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#define M_DUART_IP0_CHNG_ENA _SB_MAKEMASK1(0)
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#define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1)
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#define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2)
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#define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3)
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#define M_DUART_ACR_RESERVED _SB_MAKEMASK(4,4)
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#define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0)
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#define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2)
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/*
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* DUART Interrupt Status Register (Table 10-16)
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* Register: DUART_ISR
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*/
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#define M_DUART_ISR_TX_A _SB_MAKEMASK1(0)
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#define S_DUART_ISR_RX_A 1
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#define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A)
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#define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x,S_DUART_ISR_RX_A)
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#define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x,S_DUART_ISR_RX_A,M_DUART_ISR_RX_A)
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#define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2)
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#define M_DUART_ISR_IN_A _SB_MAKEMASK1(3)
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#define M_DUART_ISR_ALL_A _SB_MAKEMASK(4,0)
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#define M_DUART_ISR_TX_B _SB_MAKEMASK1(4)
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#define M_DUART_ISR_RX_B _SB_MAKEMASK1(5)
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#define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6)
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#define M_DUART_ISR_IN_B _SB_MAKEMASK1(7)
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#define M_DUART_ISR_ALL_B _SB_MAKEMASK(4,4)
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/*
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* DUART Channel A Interrupt Status Register (Table 10-17)
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* DUART Channel B Interrupt Status Register (Table 10-18)
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* Register: DUART_ISR_A
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* Register: DUART_ISR_B
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*/
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#define M_DUART_ISR_TX _SB_MAKEMASK1(0)
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#define M_DUART_ISR_RX _SB_MAKEMASK1(1)
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#define M_DUART_ISR_BRK _SB_MAKEMASK1(2)
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#define M_DUART_ISR_IN _SB_MAKEMASK1(3)
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#define M_DUART_ISR_ALL _SB_MAKEMASK(4,0)
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#define M_DUART_ISR_RESERVED _SB_MAKEMASK(4,4)
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/*
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* DUART Interrupt Mask Register (Table 10-19)
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* Register: DUART_IMR
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*/
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#define M_DUART_IMR_TX_A _SB_MAKEMASK1(0)
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#define M_DUART_IMR_RX_A _SB_MAKEMASK1(1)
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#define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2)
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#define M_DUART_IMR_IN_A _SB_MAKEMASK1(3)
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#define M_DUART_IMR_ALL_A _SB_MAKEMASK(4,0)
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#define M_DUART_IMR_TX_B _SB_MAKEMASK1(4)
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#define M_DUART_IMR_RX_B _SB_MAKEMASK1(5)
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#define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6)
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#define M_DUART_IMR_IN_B _SB_MAKEMASK1(7)
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#define M_DUART_IMR_ALL_B _SB_MAKEMASK(4,4)
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/*
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* DUART Channel A Interrupt Mask Register (Table 10-20)
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* DUART Channel B Interrupt Mask Register (Table 10-21)
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* Register: DUART_IMR_A
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* Register: DUART_IMR_B
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*/
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#define M_DUART_IMR_TX _SB_MAKEMASK1(0)
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#define M_DUART_IMR_RX _SB_MAKEMASK1(1)
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#define M_DUART_IMR_BRK _SB_MAKEMASK1(2)
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#define M_DUART_IMR_IN _SB_MAKEMASK1(3)
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#define M_DUART_IMR_ALL _SB_MAKEMASK(4,0)
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#define M_DUART_IMR_RESERVED _SB_MAKEMASK(4,4)
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/*
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* DUART Output Port Set Register (Table 10-22)
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* Register: DUART_SET_OPR
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*/
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#define M_DUART_SET_OPR0 _SB_MAKEMASK1(0)
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#define M_DUART_SET_OPR1 _SB_MAKEMASK1(1)
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#define M_DUART_SET_OPR2 _SB_MAKEMASK1(2)
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#define M_DUART_SET_OPR3 _SB_MAKEMASK1(3)
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#define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4,4)
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/*
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* DUART Output Port Clear Register (Table 10-23)
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* Register: DUART_CLEAR_OPR
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*/
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#define M_DUART_CLR_OPR0 _SB_MAKEMASK1(0)
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#define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1)
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#define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2)
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#define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3)
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#define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4,4)
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/*
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* DUART Output Port RTS Register (Table 10-24)
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* Register: DUART_OUT_PORT
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*/
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#define M_DUART_OUT_PIN_SET0 _SB_MAKEMASK1(0)
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#define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1)
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#define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2)
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#define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3)
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#define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4,4)
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#define M_DUART_OUT_PIN_SET(chan) \
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(chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1)
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#define M_DUART_OUT_PIN_CLR(chan) \
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(chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1)
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#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
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/*
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* Full Interrupt Control Register
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*/
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#define S_DUART_SIG_FULL _SB_MAKE64(0)
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#define M_DUART_SIG_FULL _SB_MAKEMASK(4,S_DUART_SIG_FULL)
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#define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x,S_DUART_SIG_FULL)
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#define G_DUART_SIG_FULL(x) _SB_GETVALUE(x,S_DUART_SIG_FULL,M_DUART_SIG_FULL)
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#define S_DUART_INT_TIME _SB_MAKE64(4)
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#define M_DUART_INT_TIME _SB_MAKEMASK(4,S_DUART_INT_TIME)
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#define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x,S_DUART_INT_TIME)
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#define G_DUART_INT_TIME(x) _SB_GETVALUE(x,S_DUART_INT_TIME,M_DUART_INT_TIME)
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#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
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/* ********************************************************************** */
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#endif
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