mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-11-01 10:33:27 +00:00
57d84906f0
As of git commit 1844c9bc0b head64.S/head31.S
are not included in head.S anymore but build as an extra object. This breaks
shared kernel support because the .org statement in head64.S/head31.S for
CONFIG_SHARED_KERNEL=y will have a different effect. The end address of the
head.text section in head.o will be added to the .org value, to compensate
for this subtract 0x11000 to get the required value of 0x100000 again.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
113 lines
3 KiB
ArmAsm
113 lines
3 KiB
ArmAsm
/*
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* arch/s390/kernel/head31.S
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*
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* Copyright (C) IBM Corp. 2005,2010
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*
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* Author(s): Hartmut Penner <hp@de.ibm.com>
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* Martin Schwidefsky <schwidefsky@de.ibm.com>
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* Rob van der Heij <rvdhei@iae.nl>
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* Heiko Carstens <heiko.carstens@de.ibm.com>
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*
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*/
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#include <linux/init.h>
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#include <asm/asm-offsets.h>
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#include <asm/thread_info.h>
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#include <asm/page.h>
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__HEAD
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.globl startup_continue
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startup_continue:
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basr %r13,0 # get base
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.LPG1:
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l %r1,.Lbase_cc-.LPG1(%r13)
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mvc 0(8,%r1),__LC_LAST_UPDATE_CLOCK
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lctl %c0,%c15,.Lctl-.LPG1(%r13) # load control registers
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l %r12,.Lparmaddr-.LPG1(%r13) # pointer to parameter area
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# move IPL device to lowcore
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#
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# Setup stack
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#
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l %r15,.Linittu-.LPG1(%r13)
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st %r15,__LC_THREAD_INFO # cache thread info in lowcore
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mvc __LC_CURRENT(4),__TI_task(%r15)
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ahi %r15,1<<(PAGE_SHIFT+THREAD_ORDER) # init_task_union+THREAD_SIZE
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st %r15,__LC_KERNEL_STACK # set end of kernel stack
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ahi %r15,-96
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#
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# Save ipl parameters, clear bss memory, initialize storage key for kernel pages,
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# and create a kernel NSS if the SAVESYS= parm is defined
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#
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l %r14,.Lstartup_init-.LPG1(%r13)
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basr %r14,%r14
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lpsw .Lentry-.LPG1(13) # jump to _stext in primary-space,
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# virtual and never return ...
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.align 8
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.Lentry:.long 0x00080000,0x80000000 + _stext
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.Lctl: .long 0x04b50002 # cr0: various things
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.long 0 # cr1: primary space segment table
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.long .Lduct # cr2: dispatchable unit control table
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.long 0 # cr3: instruction authorization
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.long 0 # cr4: instruction authorization
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.long .Lduct # cr5: primary-aste origin
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.long 0 # cr6: I/O interrupts
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.long 0 # cr7: secondary space segment table
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.long 0 # cr8: access registers translation
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.long 0 # cr9: tracing off
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.long 0 # cr10: tracing off
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.long 0 # cr11: tracing off
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.long 0 # cr12: tracing off
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.long 0 # cr13: home space segment table
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.long 0xc0000000 # cr14: machine check handling off
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.long 0 # cr15: linkage stack operations
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.Lmchunk:.long memory_chunk
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.Lbss_bgn: .long __bss_start
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.Lbss_end: .long _end
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.Lparmaddr: .long PARMAREA
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.Linittu: .long init_thread_union
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.Lstartup_init:
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.long startup_init
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.align 64
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.Lduct: .long 0,0,0,0,.Lduald,0,0,0
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.long 0,0,0,0,0,0,0,0
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.align 128
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.Lduald:.rept 8
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.long 0x80000000,0,0,0 # invalid access-list entries
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.endr
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.Lbase_cc:
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.long sched_clock_base_cc
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.globl _ehead
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_ehead:
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#ifdef CONFIG_SHARED_KERNEL
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.org 0x100000 - 0x11000 # head.o ends at 0x11000
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#endif
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#
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# startup-code, running in absolute addressing mode
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#
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.globl _stext
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_stext: basr %r13,0 # get base
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.LPG3:
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# check control registers
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stctl %c0,%c15,0(%r15)
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oi 2(%r15),0x40 # enable sigp emergency signal
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oi 0(%r15),0x10 # switch on low address protection
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lctl %c0,%c15,0(%r15)
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#
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lam 0,15,.Laregs-.LPG3(%r13) # load access regs needed by uaccess
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l %r14,.Lstart-.LPG3(%r13)
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basr %r14,%r14 # call start_kernel
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#
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# We returned from start_kernel ?!? PANIK
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#
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basr %r13,0
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lpsw .Ldw-.(%r13) # load disabled wait psw
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#
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.align 8
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.Ldw: .long 0x000a0000,0x00000000
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.Lstart:.long start_kernel
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.Laregs:.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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