mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-10-31 18:09:19 +00:00
bab2dc64e7
Underrun would cause resetting of CSC registers thereby causing black screen. Now schedule work to program CSC registers in underrun interrupt handler. Change-Id: I9f5cc8ddbe9afbfd36d65601b66e8da5e7ec6e95 Signed-off-by: Krishna Chaitanya Parimi <cparimi@codeaurora.org>
390 lines
8.3 KiB
C
390 lines
8.3 KiB
C
/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef MDP3_DMA_H
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#define MDP3_DMA_H
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#include <linux/notifier.h>
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#include <linux/sched.h>
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#include <linux/msm_mdp.h>
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#define MDP_HISTOGRAM_BL_SCALE_MAX 1024
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#define MDP_HISTOGRAM_BL_LEVEL_MAX 255
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#define MDP_HISTOGRAM_FRAME_COUNT_MAX 0x20
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#define MDP_HISTOGRAM_BIT_MASK_MAX 0x4
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#define MDP_HISTOGRAM_CSC_MATRIX_MAX 0x2000
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#define MDP_HISTOGRAM_CSC_VECTOR_MAX 0x200
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#define MDP_HISTOGRAM_BIN_NUM 32
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#define MDP_LUT_SIZE 256
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enum {
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MDP3_DMA_P,
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MDP3_DMA_S,
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MDP3_DMA_E,
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MDP3_DMA_MAX
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};
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enum {
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MDP3_DMA_CAP_CURSOR = 0x1,
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MDP3_DMA_CAP_COLOR_CORRECTION = 0x2,
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MDP3_DMA_CAP_HISTOGRAM = 0x4,
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MDP3_DMA_CAP_GAMMA_CORRECTION = 0x8,
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MDP3_DMA_CAP_DITHER = 0x10,
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MDP3_DMA_CAP_ALL = 0x1F
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};
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enum {
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MDP3_DMA_OUTPUT_SEL_AHB,
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MDP3_DMA_OUTPUT_SEL_DSI_CMD,
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MDP3_DMA_OUTPUT_SEL_LCDC,
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MDP3_DMA_OUTPUT_SEL_DSI_VIDEO,
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MDP3_DMA_OUTPUT_SEL_MAX
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};
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enum {
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MDP3_DMA_IBUF_FORMAT_RGB888,
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MDP3_DMA_IBUF_FORMAT_RGB565,
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MDP3_DMA_IBUF_FORMAT_XRGB8888,
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MDP3_DMA_IBUF_FORMAT_UNDEFINED
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};
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enum {
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MDP3_DMA_OUTPUT_PACK_PATTERN_RGB = 0x21,
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MDP3_DMA_OUTPUT_PACK_PATTERN_RBG = 0x24,
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MDP3_DMA_OUTPUT_PACK_PATTERN_BGR = 0x12,
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MDP3_DMA_OUTPUT_PACK_PATTERN_BRG = 0x18,
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MDP3_DMA_OUTPUT_PACK_PATTERN_GBR = 0x06,
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MDP3_DMA_OUTPUT_PACK_PATTERN_GRB = 0x09,
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};
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enum {
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MDP3_DMA_OUTPUT_PACK_ALIGN_LSB,
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MDP3_DMA_OUTPUT_PACK_ALIGN_MSB
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};
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enum {
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MDP3_DMA_OUTPUT_COMP_BITS_4, /*4 bits per color component*/
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MDP3_DMA_OUTPUT_COMP_BITS_5,
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MDP3_DMA_OUTPUT_COMP_BITS_6,
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MDP3_DMA_OUTPUT_COMP_BITS_8,
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};
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enum {
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MDP3_DMA_CURSOR_FORMAT_ARGB888,
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};
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enum {
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MDP3_DMA_COLOR_CORRECT_SET_1,
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MDP3_DMA_COLOR_CORRECT_SET_2
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};
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enum {
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MDP3_DMA_LUT_POSITION_PRE,
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MDP3_DMA_LUT_POSITION_POST
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};
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enum {
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MDP3_DMA_LUT_DISABLE = 0x0,
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MDP3_DMA_LUT_ENABLE_C0 = 0x01,
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MDP3_DMA_LUT_ENABLE_C1 = 0x02,
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MDP3_DMA_LUT_ENABLE_C2 = 0x04,
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MDP3_DMA_LUT_ENABLE_ALL = 0x07,
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};
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enum {
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MDP3_DMA_HISTOGRAM_BIT_MASK_NONE = 0X0,
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MDP3_DMA_HISTOGRAM_BIT_MASK_ONE_MSB = 0x1,
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MDP3_DMA_HISTOGRAM_BIT_MASK_TWO_MSB = 0x2,
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MDP3_DMA_HISTOGRAM_BIT_MASK_THREE_MSB = 0x3
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};
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enum {
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MDP3_DMA_COLOR_FLIP_NONE,
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MDP3_DMA_COLOR_FLIP_COMP1 = 0x1,
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MDP3_DMA_COLOR_FLIP_COMP2 = 0x2,
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MDP3_DMA_COLOR_FLIP_COMP3 = 0x4,
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};
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enum {
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MDP3_DMA_CURSOR_BLEND_NONE = 0x0,
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MDP3_DMA_CURSOR_BLEND_PER_PIXEL_ALPHA = 0x3,
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MDP3_DMA_CURSOR_BLEND_CONSTANT_ALPHA = 0x5,
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MDP3_DMA_CURSOR_BLEND_COLOR_KEYING = 0x9
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};
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enum {
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MDP3_DMA_HISTO_OP_START,
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MDP3_DMA_HISTO_OP_STOP,
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MDP3_DMA_HISTO_OP_CANCEL,
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MDP3_DMA_HISTO_OP_RESET
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};
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enum {
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MDP3_DMA_HISTO_STATE_UNKNOWN,
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MDP3_DMA_HISTO_STATE_IDLE,
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MDP3_DMA_HISTO_STATE_RESET,
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MDP3_DMA_HISTO_STATE_START,
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MDP3_DMA_HISTO_STATE_READY,
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};
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enum {
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MDP3_DMA_CALLBACK_TYPE_VSYNC = 0x01,
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MDP3_DMA_CALLBACK_TYPE_DMA_DONE = 0x02,
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MDP3_DMA_CALLBACK_TYPE_HIST_RESET_DONE = 0x04,
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MDP3_DMA_CALLBACK_TYPE_HIST_DONE = 0x08,
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};
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struct mdp3_dma_source {
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u32 format;
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int width;
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int height;
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int x;
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int y;
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dma_addr_t buf;
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int stride;
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int vsync_count;
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int vporch;
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};
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struct mdp3_dma_output_config {
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int dither_en;
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u32 out_sel;
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u32 bit_mask_polarity;
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u32 color_components_flip;
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u32 pack_pattern;
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u32 pack_align;
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u32 color_comp_out_bits;
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};
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struct mdp3_dma_cursor_blend_config {
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u32 mode;
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u32 transparent_color; /*color keying*/
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u32 transparency_mask;
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u32 constant_alpha;
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};
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struct mdp3_dma_cursor {
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int enable; /* enable cursor or not*/
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u32 format;
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int width;
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int height;
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int x;
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int y;
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void *buf;
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struct mdp3_dma_cursor_blend_config blend_config;
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};
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struct mdp3_dma_ccs {
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u32 *mv; /*set1 matrix vector, 3x3 */
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u32 *pre_bv; /*pre-bias vector for set1, 1x3*/
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u32 *post_bv; /*post-bias vecotr for set1, */
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u32 *pre_lv; /*pre-limit vector for set 1, 1x6*/
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u32 *post_lv;
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};
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struct mdp3_dma_lut_config {
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int lut_enable;
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u32 lut_sel;
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u32 lut_position;
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bool lut_dirty;
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};
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struct mdp3_dma_color_correct_config {
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int ccs_enable;
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u32 post_limit_sel;
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u32 pre_limit_sel;
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u32 post_bias_sel;
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u32 pre_bias_sel;
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u32 ccs_sel;
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bool ccs_dirty;
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};
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struct mdp3_dma_histogram_config {
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int frame_count;
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u32 bit_mask_polarity;
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u32 bit_mask;
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int auto_clear_en;
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};
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struct mdp3_dma_histogram_data {
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u32 r_data[MDP_HISTOGRAM_BIN_NUM];
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u32 g_data[MDP_HISTOGRAM_BIN_NUM];
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u32 b_data[MDP_HISTOGRAM_BIN_NUM];
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u32 extra[2];
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};
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struct mdp3_notification {
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void (*handler)(void *arg);
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void *arg;
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};
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struct mdp3_tear_check {
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int frame_rate;
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bool hw_vsync_mode;
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u32 tear_check_en;
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u32 sync_cfg_height;
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u32 vsync_init_val;
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u32 sync_threshold_start;
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u32 sync_threshold_continue;
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u32 start_pos;
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u32 rd_ptr_irq;
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u32 refx100;
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};
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struct mdp3_rect {
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u32 x;
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u32 y;
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u32 w;
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u32 h;
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};
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struct mdp3_intf;
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struct mdp3_dma {
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u32 dma_sel;
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u32 capability;
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int in_use;
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int available;
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spinlock_t dma_lock;
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spinlock_t histo_lock;
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struct completion vsync_comp;
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struct completion dma_comp;
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struct completion histo_comp;
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struct mdp3_notification vsync_client;
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struct mdp3_notification dma_notifier_client;
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struct mdp3_dma_output_config output_config;
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struct mdp3_dma_source source_config;
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struct mdp3_dma_cursor cursor;
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struct mdp3_dma_color_correct_config ccs_config;
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struct mdp_csc_cfg_data ccs_cache;
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int cc_vect_sel;
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struct work_struct underrun_work;
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struct mutex pp_lock;
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struct mdp3_dma_lut_config lut_config;
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struct mdp3_dma_histogram_config histogram_config;
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int histo_state;
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struct mdp3_dma_histogram_data histo_data;
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unsigned int vsync_status;
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bool update_src_cfg;
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bool has_panic_ctrl;
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struct mdp3_rect roi;
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u32 lut_sts;
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struct fb_cmap *gc_cmap;
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struct fb_cmap *hist_cmap;
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bool (*busy)(void);
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int (*dma_config)(struct mdp3_dma *dma,
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struct mdp3_dma_source *source_config,
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struct mdp3_dma_output_config *output_config,
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bool splash_screen_active);
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int (*dma_sync_config)(struct mdp3_dma *dma, struct mdp3_dma_source
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*source_config, struct mdp3_tear_check *te);
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void (*dma_config_source)(struct mdp3_dma *dma);
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int (*start)(struct mdp3_dma *dma, struct mdp3_intf *intf);
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int (*stop)(struct mdp3_dma *dma, struct mdp3_intf *intf);
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int (*config_cursor)(struct mdp3_dma *dma,
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struct mdp3_dma_cursor *cursor);
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int (*config_ccs)(struct mdp3_dma *dma,
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struct mdp3_dma_color_correct_config *config,
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struct mdp3_dma_ccs *ccs);
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int (*config_lut)(struct mdp3_dma *dma,
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struct mdp3_dma_lut_config *config,
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struct fb_cmap *cmap);
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int (*update)(struct mdp3_dma *dma,
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void *buf, struct mdp3_intf *intf, void *data);
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int (*update_cursor)(struct mdp3_dma *dma, int x, int y);
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int (*get_histo)(struct mdp3_dma *dma);
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int (*config_histo)(struct mdp3_dma *dma,
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struct mdp3_dma_histogram_config *histo_config);
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int (*histo_op)(struct mdp3_dma *dma, u32 op);
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void (*vsync_enable)(struct mdp3_dma *dma,
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struct mdp3_notification *vsync_client);
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void (*dma_done_notifier)(struct mdp3_dma *dma,
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struct mdp3_notification *dma_client);
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};
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struct mdp3_video_intf_cfg {
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int hsync_period;
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int hsync_pulse_width;
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int vsync_period;
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int vsync_pulse_width;
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int display_start_x;
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int display_end_x;
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int display_start_y;
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int display_end_y;
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int active_start_x;
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int active_end_x;
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int active_h_enable;
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int active_start_y;
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int active_end_y;
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int active_v_enable;
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int hsync_skew;
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int hsync_polarity;
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int vsync_polarity;
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int de_polarity;
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int underflow_color;
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};
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struct mdp3_dsi_cmd_intf_cfg {
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int primary_dsi_cmd_id;
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int secondary_dsi_cmd_id;
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int dsi_cmd_tg_intf_sel;
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};
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struct mdp3_intf_cfg {
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u32 type;
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struct mdp3_video_intf_cfg video;
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struct mdp3_dsi_cmd_intf_cfg dsi_cmd;
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};
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struct mdp3_intf {
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struct mdp3_intf_cfg cfg;
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int active;
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int available;
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int in_use;
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int (*config)(struct mdp3_intf *intf, struct mdp3_intf_cfg *cfg);
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int (*start)(struct mdp3_intf *intf);
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int (*stop)(struct mdp3_intf *intf);
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};
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int mdp3_dma_init(struct mdp3_dma *dma);
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int mdp3_intf_init(struct mdp3_intf *intf);
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void mdp3_dma_callback_enable(struct mdp3_dma *dma, int type);
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void mdp3_dma_callback_disable(struct mdp3_dma *dma, int type);
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#endif /* MDP3_DMA_H */
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